From patchwork Mon Feb 4 15:28:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 2093621 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E6A86DFE82 for ; Mon, 4 Feb 2013 16:05:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D3AC4E5C2F for ; Mon, 4 Feb 2013 08:05:12 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id F0E86E6101 for ; Mon, 4 Feb 2013 07:30:19 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 04 Feb 2013 07:29:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,600,1355126400"; d="scan'208";a="257442374" Received: from unknown (HELO dyon.amr.corp.intel.com) ([10.255.12.132]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2013 07:30:10 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Feb 2013 15:28:05 +0000 Message-Id: <1359991705-5254-71-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> References: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 70/90] assembler: Move struct relocation out of relocatable instructions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Now that all instructions (relocatable or not) are struct brw_program_instructions, this means we can move the relocation specific information out the "relocatable instruction" structure. This will allow us to share the relocation information between different types of instructions. Signed-off-by: Damien Lespiau --- assembler/gen4asm.h | 5 +-- assembler/gram.y | 76 ++++++++++++++++++++++++++------------------------- assembler/main.c | 4 +- 3 files changed, 43 insertions(+), 42 deletions(-) diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 0781eaf..5673e2c 100644 --- a/assembler/gen4asm.h +++ b/assembler/gen4asm.h @@ -126,8 +126,7 @@ struct label_instruction { char *name; }; -struct relocatable_instruction { - struct brw_instruction gen; +struct relocation { char *first_reloc_target, *second_reloc_target; // JIP and UIP respectively GLint first_reloc_offset, second_reloc_offset; // in number of instructions }; @@ -141,9 +140,9 @@ struct brw_program_instruction { unsigned inst_offset; union { struct brw_instruction gen; - struct relocatable_instruction reloc; struct label_instruction label; } insn; + struct relocation reloc; struct brw_program_instruction *next; }; diff --git a/assembler/gram.y b/assembler/gram.y index f078bfe..9b90db9 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -208,14 +208,16 @@ brw_program_add_instruction(struct brw_program *p, brw_program_append_entry(p, list_entry); } -static void brw_program_add_relocatable(struct brw_program *p, - struct brw_program_instruction *reloc) +static void +brw_program_add_relocatable(struct brw_program *p, + struct brw_program_instruction *instruction) { struct brw_program_instruction *list_entry; list_entry = calloc(sizeof(struct brw_program_instruction), 1); list_entry->type = GEN4ASM_INSTRUCTION_GEN_RELOCATABLE; - list_entry->insn.reloc = reloc->insn.reloc; + list_entry->insn.gen = instruction->insn.gen; + list_entry->reloc = instruction->reloc; brw_program_append_entry(p, list_entry); } @@ -724,8 +726,8 @@ ifelseinstruction: ENDIF memset(&$$, 0, sizeof($$)); GEN(&$$)->header.opcode = $1; GEN(&$$)->header.execution_size = $2; - $$.insn.reloc.first_reloc_target = $3.reloc_target; - $$.insn.reloc.first_reloc_offset = $3.imm32; + $$.reloc.first_reloc_target = $3.reloc_target; + $$.reloc.first_reloc_offset = $3.imm32; } | ELSE execsize relativelocation instoptions { @@ -741,14 +743,14 @@ ifelseinstruction: ENDIF set_instruction_dest(&$$, &ip_dst); set_instruction_src0(&$$, &ip_src, NULL); set_instruction_src1(&$$, &$3, NULL); - $$.insn.reloc.first_reloc_target = $3.reloc_target; - $$.insn.reloc.first_reloc_offset = $3.imm32; + $$.reloc.first_reloc_target = $3.reloc_target; + $$.reloc.first_reloc_offset = $3.imm32; } else if(IS_GENp(6)) { memset(&$$, 0, sizeof($$)); GEN(&$$)->header.opcode = $1; GEN(&$$)->header.execution_size = $2; - $$.insn.reloc.first_reloc_target = $3.reloc_target; - $$.insn.reloc.first_reloc_offset = $3.imm32; + $$.reloc.first_reloc_target = $3.reloc_target; + $$.reloc.first_reloc_offset = $3.imm32; } else { error(&@1, "'ELSE' instruction is not implemented.\n"); } @@ -773,8 +775,8 @@ ifelseinstruction: ENDIF set_instruction_src0(&$$, &ip_src, NULL); set_instruction_src1(&$$, &$4, NULL); } - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; } | predicate IF execsize relativelocation relativelocation { @@ -786,10 +788,10 @@ ifelseinstruction: ENDIF set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; GEN(&$$)->header.execution_size = $3; - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; - $$.insn.reloc.second_reloc_target = $5.reloc_target; - $$.insn.reloc.second_reloc_offset = $5.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; + $$.reloc.second_reloc_target = $5.reloc_target; + $$.reloc.second_reloc_offset = $5.imm32; } ; @@ -809,8 +811,8 @@ loopinstruction: predicate WHILE execsize relativelocation instoptions GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH; set_instruction_src0(&$$, &ip_src, NULL); set_instruction_src1(&$$, &$4, NULL); - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; } else if (IS_GENp(6)) { /* Gen6 spec: dest must have the same element size as src0. @@ -819,8 +821,8 @@ loopinstruction: predicate WHILE execsize relativelocation instoptions set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; GEN(&$$)->header.execution_size = $3; - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; } else { error(&@2, "'WHILE' instruction is not implemented!\n"); } @@ -839,10 +841,10 @@ haltinstruction: predicate HALT execsize relativelocation relativelocation insto memset(&$$, 0, sizeof($$)); set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; - $$.insn.reloc.second_reloc_target = $5.reloc_target; - $$.insn.reloc.second_reloc_offset = $5.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; + $$.reloc.second_reloc_target = $5.reloc_target; + $$.reloc.second_reloc_offset = $5.imm32; dst_null_reg.width = $3; set_instruction_dest(&$$, &dst_null_reg); set_instruction_src0(&$$, &src_null_reg, NULL); @@ -856,8 +858,8 @@ multibranchinstruction: set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH; - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; dst_null_reg.width = $3; set_instruction_dest(&$$, &dst_null_reg); } @@ -868,10 +870,10 @@ multibranchinstruction: set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH; - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; - $$.insn.reloc.second_reloc_target = $5.reloc_target; - $$.insn.reloc.second_reloc_offset = $5.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; + $$.reloc.second_reloc_target = $5.reloc_target; + $$.reloc.second_reloc_offset = $5.imm32; dst_null_reg.width = $3; set_instruction_dest(&$$, &dst_null_reg); set_instruction_src0(&$$, &src_null_reg, NULL); @@ -912,8 +914,8 @@ subroutineinstruction: src0.reg.vstride = 2; /*encoded 2*/ set_instruction_src0(&$$, &src0, NULL); - $$.insn.reloc.first_reloc_target = $5.reloc_target; - $$.insn.reloc.first_reloc_offset = $5.imm32; + $$.reloc.first_reloc_target = $5.reloc_target; + $$.reloc.first_reloc_offset = $5.imm32; } | predicate RET execsize dstoperandex src instoptions { @@ -1359,8 +1361,8 @@ jumpinstruction: predicate JMPI execsize relativelocation2 set_instruction_dest(&$$, &ip_dst); set_instruction_src0(&$$, &ip_src, NULL); set_instruction_src1(&$$, &$4, NULL); - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; } ; @@ -1388,10 +1390,10 @@ breakinstruction: predicate breakop execsize relativelocation relativelocation i set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; GEN(&$$)->header.execution_size = $3; - $$.insn.reloc.first_reloc_target = $4.reloc_target; - $$.insn.reloc.first_reloc_offset = $4.imm32; - $$.insn.reloc.second_reloc_target = $5.reloc_target; - $$.insn.reloc.second_reloc_offset = $5.imm32; + $$.reloc.first_reloc_target = $4.reloc_target; + $$.reloc.first_reloc_offset = $4.imm32; + $$.reloc.second_reloc_target = $5.reloc_target; + $$.reloc.second_reloc_offset = $5.imm32; } ; diff --git a/assembler/main.c b/assembler/main.c index 8579f96..f1d78d0 100644 --- a/assembler/main.c +++ b/assembler/main.c @@ -437,8 +437,8 @@ int main(int argc, char **argv) } for (entry = compiled_program.first; entry; entry = entry->next) { - struct relocatable_instruction *reloc = &entry->insn.reloc; - struct brw_instruction *inst = &reloc->gen; + struct relocation *reloc = &entry->reloc; + struct brw_instruction *inst = &entry->insn.gen; if (!is_relocatable(entry)) continue;