From patchwork Mon Feb 4 15:28:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 2093691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id E87F03FD56 for ; Mon, 4 Feb 2013 16:08:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D12ECE5EE5 for ; Mon, 4 Feb 2013 08:08:04 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id BB65BE60F8 for ; Mon, 4 Feb 2013 07:30:21 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 04 Feb 2013 07:29:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,600,1355126400"; d="scan'208";a="257442425" Received: from unknown (HELO dyon.amr.corp.intel.com) ([10.255.12.132]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2013 07:30:20 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Feb 2013 15:28:10 +0000 Message-Id: <1359991705-5254-76-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> References: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 75/90] assembler: Introduce set_intruction_pred_cond() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This allow us to factor out the test that checks if, when using both predicates and conditional modifiers, we are using the same flag register. Also get rid of of a FIXME that we are now dealing with (the warning mentioned above). Signed-off-by: Damien Lespiau --- assembler/gram.y | 88 +++++++++++++++++++----------------------------------- 1 files changed, 31 insertions(+), 57 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index 2d72037..917bccf 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -104,6 +104,10 @@ static void set_instruction_options(struct brw_program_instruction *instr, struct options options); static void set_instruction_predicate(struct brw_program_instruction *instr, struct predicate *p); +static void set_instruction_pred_cond(struct brw_program_instruction *instr, + struct predicate *p, + struct condition *c, + YYLTYPE *location); static void set_direct_dst_operand(struct brw_reg *dst, struct brw_reg *reg, int type); static void set_direct_src_operand(struct src_operand *src, struct brw_reg *reg, @@ -992,28 +996,15 @@ unaryinstruction: { memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); - GEN(&$$)->header.destreg__conditionalmod = $3.cond; GEN(&$$)->header.saturate = $4; $6.width = $5; set_instruction_options(&$$, $8); - set_instruction_predicate(&$$, &$1); + set_instruction_pred_cond(&$$, &$1, &$3, &@3); if (set_instruction_dest(&$$, &$6) != 0) YYERROR; if (set_instruction_src0(&$$, &$7, &@7) != 0) YYERROR; - if ($3.flag_subreg_nr != -1) { - if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - ($1.flag_reg_nr != $3.flag_reg_nr || - $1.flag_subreg_nr != $3.flag_subreg_nr)) - warn(ALWAYS, &@3, "must use the same flag register if " - "both prediction and conditional modifier are " - "enabled\n"); - - GEN(&$$)->bits2.da1.flag_reg_nr = $3.flag_reg_nr; - GEN(&$$)->bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; - } - if (!IS_GENp(6) && get_type_size(GEN(&$$)->bits1.da1.dest_reg_type) * (1 << $6.width) == 64) GEN(&$$)->header.compression_control = BRW_COMPRESSION_COMPRESSED; @@ -1031,10 +1022,9 @@ binaryinstruction: { memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); - GEN(&$$)->header.destreg__conditionalmod = $3.cond; GEN(&$$)->header.saturate = $4; set_instruction_options(&$$, $9); - set_instruction_predicate(&$$, &$1); + set_instruction_pred_cond(&$$, &$1, &$3, &@3); $6.width = $5; if (set_instruction_dest(&$$, &$6) != 0) YYERROR; @@ -1043,18 +1033,6 @@ binaryinstruction: if (set_instruction_src1(&$$, &$8, &@8) != 0) YYERROR; - if ($3.flag_subreg_nr != -1) { - if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - ($1.flag_reg_nr != $3.flag_reg_nr || - $1.flag_subreg_nr != $3.flag_subreg_nr)) - warn(ALWAYS, &@3, "must use the same flag register if " - "both prediction and conditional modifier are " - "enabled\n"); - - GEN(&$$)->bits2.da1.flag_reg_nr = $3.flag_reg_nr; - GEN(&$$)->bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; - } - if (!IS_GENp(6) && get_type_size(GEN(&$$)->bits1.da1.dest_reg_type) * (1 << $6.width) == 64) GEN(&$$)->header.compression_control = BRW_COMPRESSION_COMPRESSED; @@ -1072,11 +1050,10 @@ binaryaccinstruction: { memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); - GEN(&$$)->header.destreg__conditionalmod = $3.cond; GEN(&$$)->header.saturate = $4; $6.width = $5; set_instruction_options(&$$, $9); - set_instruction_predicate(&$$, &$1); + set_instruction_pred_cond(&$$, &$1, &$3, &@3); if (set_instruction_dest(&$$, &$6) != 0) YYERROR; if (set_instruction_src0(&$$, &$7, &@7) != 0) @@ -1084,18 +1061,6 @@ binaryaccinstruction: if (set_instruction_src1(&$$, &$8, &@8) != 0) YYERROR; - if ($3.flag_subreg_nr != -1) { - if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - ($1.flag_reg_nr != $3.flag_reg_nr || - $1.flag_subreg_nr != $3.flag_subreg_nr)) - warn(ALWAYS, &@3, "must use the same flag register if " - "both prediction and conditional modifier are " - "enabled\n"); - - GEN(&$$)->bits2.da1.flag_reg_nr = $3.flag_reg_nr; - GEN(&$$)->bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; - } - if (!IS_GENp(6) && get_type_size(GEN(&$$)->bits1.da1.dest_reg_type) * (1 << $6.width) == 64) GEN(&$$)->header.compression_control = BRW_COMPRESSION_COMPRESSED; @@ -1115,10 +1080,9 @@ trinaryinstruction: { memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); + set_instruction_pred_cond(&$$, &$1, &$3, &@3); set_instruction_opcode(&$$, $2); - GEN(&$$)->header.destreg__conditionalmod = $3.cond; GEN(&$$)->header.saturate = $4; GEN(&$$)->header.execution_size = $5; @@ -1131,15 +1095,6 @@ trinaryinstruction: if (set_instruction_src2_three_src(&$$, &$9)) YYERROR; set_instruction_options(&$$, $10); - - if ($3.flag_subreg_nr != -1) { - if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - ($1.flag_reg_nr != $3.flag_reg_nr || - $1.flag_subreg_nr != $3.flag_subreg_nr)) - warn(ALWAYS, &@3, "must use the same flag register if " - "both prediction and conditional modifier are " - "enabled\n"); - } } ; @@ -2670,10 +2625,6 @@ predicate: /* empty */ | LPAREN predstate flagreg predctrl RPAREN { $$.pred_control = $4; - /* XXX: Should deal with erroring when the user tries to - * set a predicate for one flag register and conditional - * modification on the other flag register. - */ $$.flag_reg_nr = $3.nr; $$.flag_subreg_nr = $3.subnr; $$.pred_inverse = $2; @@ -3061,6 +3012,29 @@ static void set_instruction_predicate(struct brw_program_instruction *instr, GEN(instr)->bits2.da1.flag_subreg_nr = p->flag_subreg_nr; } +static void set_instruction_pred_cond(struct brw_program_instruction *instr, + struct predicate *p, + struct condition *c, + YYLTYPE *location) +{ + set_instruction_predicate(instr, p); + GEN(instr)->header.destreg__conditionalmod = c->cond; + + if (c->flag_subreg_nr == -1) + return; + + if (p->pred_control != BRW_PREDICATE_NONE && + (p->flag_reg_nr != c->flag_reg_nr || + p->flag_subreg_nr != c->flag_subreg_nr)) + { + warn(ALWAYS, location, "must use the same flag register if both " + "prediction and conditional modifier are enabled\n"); + } + + GEN(instr)->bits2.da1.flag_reg_nr = c->flag_reg_nr; + GEN(instr)->bits2.da1.flag_subreg_nr = c->flag_subreg_nr; +} + static void set_direct_dst_operand(struct brw_reg *dst, struct brw_reg *reg, int type) {