From patchwork Mon Feb 4 15:28:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 2093711 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id EC5CD3FD56 for ; Mon, 4 Feb 2013 16:08:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D4F43E5CE4 for ; Mon, 4 Feb 2013 08:08:50 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B9256E60D0 for ; Mon, 4 Feb 2013 07:30:23 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 04 Feb 2013 07:29:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,600,1355126400"; d="scan'208";a="257442442" Received: from unknown (HELO dyon.amr.corp.intel.com) ([10.255.12.132]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2013 07:30:22 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Feb 2013 15:28:12 +0000 Message-Id: <1359991705-5254-78-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> References: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 77/90] assembler: Expose setters for 3src operands X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Signed-off-by: Damien Lespiau --- assembler/brw_eu.h | 17 +++++++++++++++++ assembler/brw_eu_emit.c | 43 +++++++++++++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 8 deletions(-) diff --git a/assembler/brw_eu.h b/assembler/brw_eu.h index 6d656a4..20d4b82 100644 --- a/assembler/brw_eu.h +++ b/assembler/brw_eu.h @@ -385,6 +385,23 @@ void brw_set_uip_jip(struct brw_compile *p); uint32_t brw_swap_cmod(uint32_t cmod); +void +brw_set_3src_dest(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg dest); +void +brw_set_3src_src0(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg src0); +void +brw_set_3src_src1(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg src1); +void +brw_set_3src_src2(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg src2); + /* brw_eu_compact.c */ void brw_init_compaction_tables(struct intel_context *intel); void brw_compact_instructions(struct brw_compile *p); diff --git a/assembler/brw_eu_emit.c b/assembler/brw_eu_emit.c index c63f1fc..e6e3e10 100644 --- a/assembler/brw_eu_emit.c +++ b/assembler/brw_eu_emit.c @@ -813,15 +813,11 @@ get_3src_subreg_nr(struct brw_reg reg) } } -static struct brw_instruction *brw_alu3(struct brw_compile *p, - GLuint opcode, - struct brw_reg dest, - struct brw_reg src0, - struct brw_reg src1, - struct brw_reg src2) +void +brw_set_3src_dest(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg dest) { - struct brw_instruction *insn = next_insn(p, opcode); - gen7_convert_mrf_to_grf(p, &dest); assert(insn->header.access_mode == BRW_ALIGN_16); @@ -836,7 +832,13 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p, insn->bits1.da3src.dest_subreg_nr = dest.subnr / 16; insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask; guess_execution_size(p, insn, dest); +} +void +brw_set_3src_src0(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg src0) +{ assert(src0.file == BRW_GENERAL_REGISTER_FILE); assert(src0.address_mode == BRW_ADDRESS_DIRECT); assert(src0.nr < 128); @@ -847,7 +849,13 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p, insn->bits1.da3src.src0_abs = src0.abs; insn->bits1.da3src.src0_negate = src0.negate; insn->bits2.da3src.src0_rep_ctrl = src0.vstride == BRW_VERTICAL_STRIDE_0; +} +void +brw_set_3src_src1(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg src1) +{ assert(src1.file == BRW_GENERAL_REGISTER_FILE); assert(src1.address_mode == BRW_ADDRESS_DIRECT); assert(src1.nr < 128); @@ -859,7 +867,13 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p, insn->bits3.da3src.src1_reg_nr = src1.nr; insn->bits1.da3src.src1_abs = src1.abs; insn->bits1.da3src.src1_negate = src1.negate; +} +void +brw_set_3src_src2(struct brw_compile *p, + struct brw_instruction *insn, + struct brw_reg src2) +{ assert(src2.file == BRW_GENERAL_REGISTER_FILE); assert(src2.address_mode == BRW_ADDRESS_DIRECT); assert(src2.nr < 128); @@ -870,7 +884,20 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p, insn->bits3.da3src.src2_reg_nr = src2.nr; insn->bits1.da3src.src2_abs = src2.abs; insn->bits1.da3src.src2_negate = src2.negate; +} +static struct brw_instruction *brw_alu3(struct brw_compile *p, + GLuint opcode, + struct brw_reg dest, + struct brw_reg src0, + struct brw_reg src1, + struct brw_reg src2) +{ + struct brw_instruction *insn = next_insn(p, opcode); + brw_set_3src_dest(p, insn, dest); + brw_set_3src_src0(p, insn, src0); + brw_set_3src_src1(p, insn, src1); + brw_set_3src_src2(p, insn, src2); return insn; }