| Message ID | 1366316916-4164-4-git-send-email-kenneth@whitecape.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 18 Apr 2013, Kenneth Graunke <kenneth@whitecape.org> wrote: > Now that we have function pointers, it's cleaner to just create a new > per-platform PTE encoding function. > > This should be identical in behavior to the previous code. It does drop the extra paranoia BUG() on unknown cache level. We should have seen those by now, so I don't mind. Please drop the inline here too. Otherwise, Reviewed-by: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++++++++++++++++++++----------- > 1 file changed, 21 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index db5c654..034a502 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -53,20 +53,13 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, > > switch (level) { > case I915_CACHE_LLC_MLC: > - /* Haswell doesn't set L3 this way */ > - if (IS_HASWELL(dev)) > - pte |= GEN6_PTE_CACHE_LLC; > - else > - pte |= GEN6_PTE_CACHE_LLC_MLC; > + pte |= GEN6_PTE_CACHE_LLC_MLC; > break; > case I915_CACHE_LLC: > pte |= GEN6_PTE_CACHE_LLC; > break; > case I915_CACHE_NONE: > - if (IS_HASWELL(dev)) > - pte |= HSW_PTE_UNCACHED; > - else > - pte |= GEN6_PTE_UNCACHED; > + pte |= GEN6_PTE_UNCACHED; > break; > default: > BUG(); > @@ -96,6 +89,19 @@ static inline gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, > return pte; > } > > +static inline gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev, > + dma_addr_t addr, > + enum i915_cache_level level) > +{ > + gen6_gtt_pte_t pte = GEN6_PTE_VALID; > + pte |= GEN6_PTE_ADDR_ENCODE(addr); > + > + if (level != I915_CACHE_NONE) > + pte |= GEN6_PTE_CACHE_LLC; > + > + return pte; > +} > + > static int gen6_ppgtt_enable(struct drm_device *dev) > { > drm_i915_private_t *dev_priv = dev->dev_private; > @@ -257,7 +263,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) > first_pd_entry_in_global_pt = > gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; > > - if (IS_VALLEYVIEW(dev)) { > + if (IS_HASWELL(dev)) { > + ppgtt->pte_encode = hsw_pte_encode; > + } else if (IS_VALLEYVIEW(dev)) { > ppgtt->pte_encode = byt_pte_encode; > } else { > ppgtt->pte_encode = gen6_pte_encode; > @@ -851,7 +859,9 @@ int i915_gem_gtt_init(struct drm_device *dev) > } else { > dev_priv->gtt.gtt_probe = gen6_gmch_probe; > dev_priv->gtt.gtt_remove = gen6_gmch_remove; > - if (IS_VALLEYVIEW(dev)) { > + if (IS_HASWELL(dev)) { > + dev_priv->gtt.pte_encode = hsw_pte_encode; > + } else if (IS_VALLEYVIEW(dev)) { > dev_priv->gtt.pte_encode = byt_pte_encode; > } else { > dev_priv->gtt.pte_encode = gen6_pte_encode; > -- > 1.8.2.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index db5c654..034a502 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -53,20 +53,13 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, switch (level) { case I915_CACHE_LLC_MLC: - /* Haswell doesn't set L3 this way */ - if (IS_HASWELL(dev)) - pte |= GEN6_PTE_CACHE_LLC; - else - pte |= GEN6_PTE_CACHE_LLC_MLC; + pte |= GEN6_PTE_CACHE_LLC_MLC; break; case I915_CACHE_LLC: pte |= GEN6_PTE_CACHE_LLC; break; case I915_CACHE_NONE: - if (IS_HASWELL(dev)) - pte |= HSW_PTE_UNCACHED; - else - pte |= GEN6_PTE_UNCACHED; + pte |= GEN6_PTE_UNCACHED; break; default: BUG(); @@ -96,6 +89,19 @@ static inline gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, return pte; } +static inline gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev, + dma_addr_t addr, + enum i915_cache_level level) +{ + gen6_gtt_pte_t pte = GEN6_PTE_VALID; + pte |= GEN6_PTE_ADDR_ENCODE(addr); + + if (level != I915_CACHE_NONE) + pte |= GEN6_PTE_CACHE_LLC; + + return pte; +} + static int gen6_ppgtt_enable(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -257,7 +263,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; - if (IS_VALLEYVIEW(dev)) { + if (IS_HASWELL(dev)) { + ppgtt->pte_encode = hsw_pte_encode; + } else if (IS_VALLEYVIEW(dev)) { ppgtt->pte_encode = byt_pte_encode; } else { ppgtt->pte_encode = gen6_pte_encode; @@ -851,7 +859,9 @@ int i915_gem_gtt_init(struct drm_device *dev) } else { dev_priv->gtt.gtt_probe = gen6_gmch_probe; dev_priv->gtt.gtt_remove = gen6_gmch_remove; - if (IS_VALLEYVIEW(dev)) { + if (IS_HASWELL(dev)) { + dev_priv->gtt.pte_encode = hsw_pte_encode; + } else if (IS_VALLEYVIEW(dev)) { dev_priv->gtt.pte_encode = byt_pte_encode; } else { dev_priv->gtt.pte_encode = gen6_pte_encode;
Now that we have function pointers, it's cleaner to just create a new per-platform PTE encoding function. This should be identical in behavior to the previous code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)