From patchwork Mon Apr 22 07:53:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 2470321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 2C81CDF23A for ; Mon, 22 Apr 2013 07:53:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0589BE6655 for ; Mon, 22 Apr 2013 00:53:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from homiemail-a37.g.dreamhost.com (caiajhbdcbef.dreamhost.com [208.97.132.145]) by gabe.freedesktop.org (Postfix) with ESMTP id 4446EE65DE for ; Mon, 22 Apr 2013 00:52:41 -0700 (PDT) Received: from homiemail-a37.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a37.g.dreamhost.com (Postfix) with ESMTP id C5B1E20806C; Mon, 22 Apr 2013 00:52:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=whitecape.org; h=from:to :cc:subject:date:message-id:in-reply-to:references; s= whitecape.org; bh=JynfTvG1bZy6yYkCxDJrzgaVoEQ=; b=mcEvbZACQlKw3f JI+EBndnI9nk11o3Fwt5YobVFPf3rnbV+RM20dYKbRmKwykZbTfJZ51LNisjStyV EuEeDlmcwaV1JTWTzSLKUUa6d+Klc5weoKtKLcgjZ/NeEyPJw+VjGsipy7RkHvA0 Wclq2X1Yhs8/T89FvR9JckePHOZ3U= Received: from localhost.localdomain (static-50-43-15-186.bvtn.or.frontiernet.net [50.43.15.186]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: kenneth@whitecape.org) by homiemail-a37.g.dreamhost.com (Postfix) with ESMTPSA id 7C420208070; Mon, 22 Apr 2013 00:52:40 -0700 (PDT) From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Apr 2013 00:53:50 -0700 Message-Id: <1366617231-1075-2-git-send-email-kenneth@whitecape.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1366617231-1075-1-git-send-email-kenneth@whitecape.org> References: <1366617231-1075-1-git-send-email-kenneth@whitecape.org> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Fix page table entries for Bay Trail. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org On Bay Trail, bit 1 means "writeable by the GPU." Failing to set that means basically anything using the GPU will cause hangs. v2: Drop accidental inline keyword on byt_pte_encode. Signed-off-by: Kenneth Graunke Reviewed-by: Jani Nikula [v1] Tested-by: Daniel Leung [v1] --- drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) To address Jani's comment about PPGTT - Daniel thinks Jesse has patches for aliasing PPGTT floating around that could land at some point. Also, if we get real PPGTT, we'll also need this. Either way, setting it up is trivial and leaving it out could lead to bugs later. diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 92e147f..62058dc 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -73,6 +73,27 @@ static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, return pte; } +#define BYT_PTE_WRITEABLE (1 << 1) +#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) + +static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, + dma_addr_t addr, + enum i915_cache_level level) +{ + gen6_gtt_pte_t pte = GEN6_PTE_VALID; + pte |= GEN6_PTE_ADDR_ENCODE(addr); + + /* Mark the page as writeable. Other platforms don't have a + * setting for read-only/writable, so this matches that behavior. + */ + pte |= BYT_PTE_WRITEABLE; + + if (level != I915_CACHE_NONE) + pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; + + return pte; +} + static int gen6_ppgtt_enable(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -234,7 +255,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; - ppgtt->pte_encode = gen6_pte_encode; + if (IS_VALLEYVIEW(dev)) { + ppgtt->pte_encode = byt_pte_encode; + } else { + ppgtt->pte_encode = gen6_pte_encode; + } ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; ppgtt->enable = gen6_ppgtt_enable; ppgtt->clear_range = gen6_ppgtt_clear_range; @@ -824,7 +849,11 @@ int i915_gem_gtt_init(struct drm_device *dev) } else { dev_priv->gtt.gtt_probe = gen6_gmch_probe; dev_priv->gtt.gtt_remove = gen6_gmch_remove; - dev_priv->gtt.pte_encode = gen6_pte_encode; + if (IS_VALLEYVIEW(dev)) { + dev_priv->gtt.pte_encode = byt_pte_encode; + } else { + dev_priv->gtt.pte_encode = gen6_pte_encode; + } } ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,