From patchwork Thu May 9 17:44:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Turner X-Patchwork-Id: 2544871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id C9E393FD4E for ; Thu, 9 May 2013 17:48:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C8B7E64D1 for ; Thu, 9 May 2013 10:48:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 34C03E64D5 for ; Thu, 9 May 2013 10:47:02 -0700 (PDT) Received: by mail-pa0-f54.google.com with SMTP id kx1so2280228pab.27 for ; Thu, 09 May 2013 10:47:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=RWZyzay5XR/gvX1SLVrdy9q+jEJsA0SKXjEHcd2z1zM=; b=dkbTHLJuLs9s9FGXedB5JZicgj6LIOfJXUTelwMUlIehKI05QSfS4uk2QODjtReoSd 35timzKLGTH7PF4YXTx38enV4VH6uieKmWE60P3sll3nS+4AMnpXNY3QYExejb2RQaqU ig61YAk+t7OeTpwFR46JVQkMNIdpvm7bN74hHdDMdYSHqr/uIycsFkkdhFBvrlf0IPPR Bjeid3IRKvHr0sY8wzvawpgzuwNig018HqdO7MnmcrsYjcxK+Xh0Pu2AryZKdJSdF5CR vJYPN+ph3WBiwe1VjQXkShyXqwaPkdmcmeuQi7YHKepcwT7PRWMduwFok+qok8fB3dTP c87Q== X-Received: by 10.66.250.230 with SMTP id zf6mr14355666pac.153.1368121622021; Thu, 09 May 2013 10:47:02 -0700 (PDT) Received: from localhost (fruit.freedesktop.org. [131.252.210.190]) by mx.google.com with ESMTPSA id fp2sm3631076pbb.36.2013.05.09.10.47.00 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 10:47:01 -0700 (PDT) From: Matt Turner To: intel-gfx@lists.freedesktop.org Date: Thu, 9 May 2013 10:44:48 -0700 Message-Id: <1368121488-20531-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.8.1.5 Subject: [Intel-gfx] [PATCH intel-gpu-tools] assembler: Add support for the SENDC instruction. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org --- assembler/gram.y | 20 ++++++++++++-------- assembler/lex.l | 1 + 2 files changed, 13 insertions(+), 8 deletions(-) Reviewed-by: Damien Lespiau diff --git a/assembler/gram.y b/assembler/gram.y index 50d71d1..09f21f1 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -440,7 +440,7 @@ static void resolve_subnr(struct brw_reg *reg) %token MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2 %token AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN PLN %token ADDC BFI1 BFREV CBIT F16TO32 F32TO16 FBH FBL -%token SEND NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE +%token SEND SENDC NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE %token PUSH MREST POP WAIT DO ENDIF ILLEGAL %token MATH_INST %token MAD LRP BFE BFI2 SUBB @@ -494,6 +494,7 @@ static void resolve_subnr(struct brw_reg *reg) %type instoption %type unaryop binaryop binaryaccop breakop %type trinaryop +%type sendop %type conditionalmodifier %type predicate %type instoptions instoption_list @@ -1099,7 +1100,10 @@ trinaryinstruction: } ; -sendinstruction: predicate SEND execsize exp post_dst payload msgtarget +sendop: SEND | SENDC +; + +sendinstruction: predicate sendop execsize exp post_dst payload msgtarget MSGLEN exp RETURNLEN exp instoptions { /* Send instructions are messy. The first argument is the @@ -1163,7 +1167,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget GEN(&$$)->bits3.generic.end_of_thread = $12.end_of_thread; } } - | predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions + | predicate sendop execsize dst sendleadreg payload directsrcoperand instoptions { memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); @@ -1181,7 +1185,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget YYERROR; } - | predicate SEND execsize dst sendleadreg payload imm32reg instoptions + | predicate sendop execsize dst sendleadreg payload imm32reg instoptions { if ($7.reg.type != BRW_REGISTER_TYPE_UD && $7.reg.type != BRW_REGISTER_TYPE_D && @@ -1202,7 +1206,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget if (set_instruction_src1(&$$, &$7, &@7) != 0) YYERROR; } - | predicate SEND execsize dst sendleadreg sndopr imm32reg instoptions + | predicate sendop execsize dst sendleadreg sndopr imm32reg instoptions { struct src_operand src0; @@ -1243,7 +1247,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); } - | predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions + | predicate sendop execsize dst sendleadreg sndopr directsrcoperand instoptions { struct src_operand src0; @@ -1284,7 +1288,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget set_instruction_src1(&$$, &$7, &@7); GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); } - | predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions + | predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions { if ($8.reg.type != BRW_REGISTER_TYPE_UD && $8.reg.type != BRW_REGISTER_TYPE_D && @@ -1310,7 +1314,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK); } } - | predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions + | predicate sendop execsize dst sendleadreg payload exp directsrcoperand instoptions { memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); diff --git a/assembler/lex.l b/assembler/lex.l index 769d98b..4f1f961 100644 --- a/assembler/lex.l +++ b/assembler/lex.l @@ -129,6 +129,7 @@ yylval.integer = BRW_CHANNEL_W; "subb" { yylval.integer = BRW_OPCODE_SUBB; return SUBB; } "send" { yylval.integer = BRW_OPCODE_SEND; return SEND; } +"sendc" { yylval.integer = BRW_OPCODE_SENDC; return SENDC; } "nop" { yylval.integer = BRW_OPCODE_NOP; return NOP; } "jmpi" { yylval.integer = BRW_OPCODE_JMPI; return JMPI; } "if" { yylval.integer = BRW_OPCODE_IF; return IF; }