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[14.5/34] drm/i915: Unify PPGTT codepaths on gen6+

Message ID 1369805569-7845-1-git-send-email-ben@bwidawsk.net (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Widawsky May 29, 2013, 5:32 a.m. UTC
This will allow us to use the same code paths whether or not we have
PPGTT actually turned on. It will do all but actually enable the bits
that tell the HW to use PPGTT.

This patch also will help tie together contexts and PPGTT in the next
patch. That patch wants to disable contexts if there is no PPGTT, and we
disable PPGTT on gen6 with VT-D. Since Mesa depends on gen6+ having HW
contexts, this is a requirement.

Just compiled tested for now, I'll do more testing on it if the relevant
parties find it swallowable.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_dma.c     | 3 ++-
 drivers/gpu/drm/i915/i915_gem.c     | 6 +++++-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 3 files changed, 9 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 3ae8298..ad7f3ce 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -975,7 +975,8 @@  static int i915_getparam(struct drm_device *dev, void *data,
 		value = HAS_LLC(dev);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
+		if (intel_enable_ppgtt(dev) && dev_priv->mm.aliasing_ppgtt)
+			value = 1;
 		break;
 	case I915_PARAM_HAS_WAIT_TIMEOUT:
 		value = 1;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fc35447..42beb50 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4072,7 +4072,11 @@  int i915_gem_init(struct drm_device *dev)
 			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
 	}
 
-	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
+	/* NB: In order to keep the code paths for all platforms with PPGTT the
+	 * same, we run through this next section regardless, but don't actually
+	 * enable the PPGTT via GFX_MODE.
+	 */
+	if (HAS_ALIASING_PPGTT(dev)) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		i915_gem_setup_global_gtt(dev, 0, dev_priv->gtt.mappable_end,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a126955..d1a41f7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -154,7 +154,8 @@  static int gen6_ppgtt_enable(struct drm_device *dev)
 		ecochk = I915_READ(GAM_ECOCHK);
 		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 				       ECOCHK_PPGTT_CACHE64B);
-		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+		if (intel_enable_ppgtt(dev))
+			I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	} else if (INTEL_INFO(dev)->gen >= 7) {
 		uint32_t ecochk, ecobits;