From patchwork Wed May 29 05:32:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 2627881 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id DFCCC40077 for ; Wed, 29 May 2013 05:30:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 908B7E5D3D for ; Tue, 28 May 2013 22:30:18 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from shiva.localdomain (unknown [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id ED904E5CB1 for ; Tue, 28 May 2013 22:30:05 -0700 (PDT) Received: by shiva.localdomain (Postfix, from userid 1005) id 4A2B08874B; Wed, 29 May 2013 05:30:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on shiva.chad-versace.us X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00, URIBL_BLOCKED autolearn=ham version=3.3.2 Received: from lundgren.kumite (c-24-21-100-90.hsd1.or.comcast.net [24.21.100.90]) by shiva.localdomain (Postfix) with ESMTPSA id C393E8862F; Wed, 29 May 2013 05:30:03 +0000 (UTC) From: Ben Widawsky To: Intel GFX Date: Tue, 28 May 2013 22:32:49 -0700 Message-Id: <1369805569-7845-1-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.8.3 In-Reply-To: <1369510028-3343-16-git-send-email-ben@bwidawsk.net> References: <1369510028-3343-16-git-send-email-ben@bwidawsk.net> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 14.5/34] drm/i915: Unify PPGTT codepaths on gen6+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This will allow us to use the same code paths whether or not we have PPGTT actually turned on. It will do all but actually enable the bits that tell the HW to use PPGTT. This patch also will help tie together contexts and PPGTT in the next patch. That patch wants to disable contexts if there is no PPGTT, and we disable PPGTT on gen6 with VT-D. Since Mesa depends on gen6+ having HW contexts, this is a requirement. Just compiled tested for now, I'll do more testing on it if the relevant parties find it swallowable. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_dma.c | 3 ++- drivers/gpu/drm/i915/i915_gem.c | 6 +++++- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 3ae8298..ad7f3ce 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -975,7 +975,8 @@ static int i915_getparam(struct drm_device *dev, void *data, value = HAS_LLC(dev); break; case I915_PARAM_HAS_ALIASING_PPGTT: - value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; + if (intel_enable_ppgtt(dev) && dev_priv->mm.aliasing_ppgtt) + value = 1; break; case I915_PARAM_HAS_WAIT_TIMEOUT: value = 1; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fc35447..42beb50 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4072,7 +4072,11 @@ int i915_gem_init(struct drm_device *dev) DRM_DEBUG_DRIVER("allow wake ack timed out\n"); } - if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { + /* NB: In order to keep the code paths for all platforms with PPGTT the + * same, we run through this next section regardless, but don't actually + * enable the PPGTT via GFX_MODE. + */ + if (HAS_ALIASING_PPGTT(dev)) { struct i915_hw_ppgtt *ppgtt; i915_gem_setup_global_gtt(dev, 0, dev_priv->gtt.mappable_end, diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a126955..d1a41f7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -154,7 +154,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev) ecochk = I915_READ(GAM_ECOCHK); I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); - I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); + if (intel_enable_ppgtt(dev)) + I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); } else if (INTEL_INFO(dev)->gen >= 7) { uint32_t ecochk, ecobits;