From patchwork Thu Jun 27 23:30:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 2796101 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BF4C99F3A0 for ; Thu, 27 Jun 2013 23:35:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB2DC201CA for ; Thu, 27 Jun 2013 23:35:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DED3D201C8 for ; Thu, 27 Jun 2013 23:35:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3B15E6494 for ; Thu, 27 Jun 2013 16:35:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from shiva.localdomain (unknown [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id E9FE2E6423 for ; Thu, 27 Jun 2013 16:28:18 -0700 (PDT) Received: by shiva.localdomain (Postfix, from userid 99) id BC5D8886A6; Thu, 27 Jun 2013 23:28:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from lundgren.jf.intel.com (jfdmzpr02-ext.jf.intel.com [134.134.137.71]) by shiva.localdomain (Postfix) with ESMTPSA id 395E08867F; Thu, 27 Jun 2013 23:28:18 +0000 (UTC) From: Ben Widawsky To: Intel GFX Date: Thu, 27 Jun 2013 16:30:14 -0700 Message-Id: <1372375867-1003-14-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1372375867-1003-1-git-send-email-ben@bwidawsk.net> References: <1372375867-1003-1-git-send-email-ben@bwidawsk.net> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 13/66] drm/i915: Unify PPGTT codepaths on gen6+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Virus-Scanned: ClamAV using ClamSMTP This will allow us to use the same code paths whether or not we have PPGTT actually turned on. It will do all but actually enable the bits that tell the HW to use PPGTT. This patch also will help tie together contexts and PPGTT in the next patch. That patch wants to disable contexts if there is no PPGTT, and we disable PPGTT on gen6 with VT-D. Since Mesa depends on gen6+ having HW contexts, this is a requirement. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_dma.c | 3 ++- drivers/gpu/drm/i915/i915_gem.c | 6 +++++- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index adb319b..cb08907 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -977,7 +977,8 @@ static int i915_getparam(struct drm_device *dev, void *data, value = HAS_LLC(dev); break; case I915_PARAM_HAS_ALIASING_PPGTT: - value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; + if (intel_enable_ppgtt(dev) && dev_priv->mm.aliasing_ppgtt) + value = 1; break; case I915_PARAM_HAS_WAIT_TIMEOUT: value = 1; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f3d6059..a337ce1 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4220,7 +4220,11 @@ int i915_gem_init(struct drm_device *dev) DRM_DEBUG_DRIVER("allow wake ack timed out\n"); } - if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { + /* NB: In order to keep the code paths for all platforms with PPGTT the + * same, we run through this next section regardless, but don't actually + * enable the PPGTT via GFX_MODE. + */ + if (HAS_ALIASING_PPGTT(dev)) { struct i915_hw_ppgtt *ppgtt; i915_gem_setup_global_gtt(dev, 0, dev_priv->gtt.mappable_end, diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 87e5c7a..16a8486 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -154,7 +154,9 @@ static int gen6_ppgtt_enable(struct drm_device *dev) ecochk = I915_READ(GAM_ECOCHK); I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); - I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); + if (intel_enable_ppgtt(dev)) + I915_WRITE(GFX_MODE, + _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); } else if (INTEL_INFO(dev)->gen >= 7) { uint32_t ecochk, ecobits;