From patchwork Thu Jun 27 23:30:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 2796041 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2000E9F3A0 for ; Thu, 27 Jun 2013 23:32:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 00C80201CA for ; Thu, 27 Jun 2013 23:32:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0FCD2201C8 for ; Thu, 27 Jun 2013 23:32:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D9370E5C48 for ; Thu, 27 Jun 2013 16:32:25 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from shiva.localdomain (unknown [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 1416CE5C48 for ; Thu, 27 Jun 2013 16:28:17 -0700 (PDT) Received: by shiva.localdomain (Postfix, from userid 99) id 65F29886AE; Thu, 27 Jun 2013 23:28:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from lundgren.jf.intel.com (jfdmzpr02-ext.jf.intel.com [134.134.137.71]) by shiva.localdomain (Postfix) with ESMTPSA id 6D98A8862F; Thu, 27 Jun 2013 23:28:14 +0000 (UTC) From: Ben Widawsky To: Intel GFX Date: Thu, 27 Jun 2013 16:30:07 -0700 Message-Id: <1372375867-1003-7-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1372375867-1003-1-git-send-email-ben@bwidawsk.net> References: <1372375867-1003-1-git-send-email-ben@bwidawsk.net> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 06/66] drm/i915: Conditionally use guard page based on PPGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Virus-Scanned: ClamAV using ClamSMTP The PPGTT PDEs serve as the guard page (as long as they remain at the top) so we don't need yet another guard page. Note that there is a potential issue if the aliasing PPGTT (and later, the default context) relinquish this part of the GGTT. We should be able to assert that won't happen however. While there, add some comments for the setup_global_gtt function which started getting complicated. The reason I've opted not to leave out the guard_page argument is that in order to support dri1, we call the setup function, and I didn't like to have to clear the guard page in more than 1 location. Signed-off-by: Ben Widawsky Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 27 ++++++++++++++++++++++----- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b709712..c677d6c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1852,7 +1852,8 @@ void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); void i915_gem_init_global_gtt(struct drm_device *dev); void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, - unsigned long mappable_end, unsigned long end); + unsigned long mappable_end, unsigned long end, + unsigned long guard_size); int i915_gem_gtt_init(struct drm_device *dev); static inline void i915_gem_chipset_flush(struct drm_device *dev) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6806bb9..629e047 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -158,8 +158,8 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data, mutex_lock(&dev->struct_mutex); i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, - args->gtt_end); - dev_priv->gtt.mappable_end = args->gtt_end; + args->gtt_end, PAGE_SIZE); + dev_priv->gtt.mappable_end = args->gtt_end - PAGE_SIZE; mutex_unlock(&dev->struct_mutex); return 0; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0fce8d0..fb30d65 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -613,10 +613,23 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node, *end -= 4096; } } + +/** + * i915_gem_setup_global_gtt() setup an allocator for the global GTT with the + * given parameters and initialize all PTEs to point to the scratch page. + * + * @dev + * @start - first offset of managed GGTT space + * @mappable_end - Last offset of the aperture mapped region + * @end - Last offset that can be accessed by the allocator + * @guard_size - Size to initialize to scratch after end. (Currently only used + * for prefetching case) + */ void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, unsigned long mappable_end, - unsigned long end) + unsigned long end, + unsigned long guard_size) { /* Let GEM Manage all of the aperture. * @@ -634,8 +647,11 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, BUG_ON(mappable_end > end); + if (WARN_ON(guard_size & ~PAGE_MASK)) + guard_size = round_up(guard_size, PAGE_SIZE); + /* Subtract the guard page ... */ - drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); + drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - guard_size); if (!HAS_LLC(dev)) dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; @@ -665,7 +681,8 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, } /* And finally clear the reserved guard page */ - dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); + dev_priv->gtt.gtt_clear_range(dev, (end - guard_size) / PAGE_SIZE, + guard_size / PAGE_SIZE); } static bool @@ -700,7 +717,7 @@ void i915_gem_init_global_gtt(struct drm_device *dev) gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; } - i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); + i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size, 0); ret = i915_gem_init_aliasing_ppgtt(dev); if (!ret) @@ -710,7 +727,7 @@ void i915_gem_init_global_gtt(struct drm_device *dev) drm_mm_takedown(&dev_priv->mm.gtt_space); gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; } - i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); + i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size, PAGE_SIZE); } static int setup_scratch_page(struct drm_device *dev)