From patchwork Wed Jul 17 15:36:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2828792 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E41C2C0AB2 for ; Wed, 17 Jul 2013 15:37:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 180A520371 for ; Wed, 17 Jul 2013 15:37:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CE75920362 for ; Wed, 17 Jul 2013 15:37:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D897EE639A for ; Wed, 17 Jul 2013 08:37:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f176.google.com (mail-pd0-f176.google.com [209.85.192.176]) by gabe.freedesktop.org (Postfix) with ESMTP id CF1C9E60B3 for ; Wed, 17 Jul 2013 08:36:25 -0700 (PDT) Received: by mail-pd0-f176.google.com with SMTP id t12so1955470pdi.21 for ; Wed, 17 Jul 2013 08:36:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=R8a8GhFzOkLx83/U5t8k9HMvQL3rPngAEUC4e+xshx8=; b=eJv+6gkp9Mc4qVyo+ZombDgO2IOJrtk475XoR+oQM4trGRS54b+S7LteIzRVPPlZ+d 7wHVb0xeZnd4qYgMxniV89RK6KeOHEXjAINMXE4llESnHwXSNn73JuwO4OzLMi8v7Jnr UNzRsQe5tQKlPFrq09zo1z25Cq9aStqSkkq880Vpgm4Q/12m1AVLDLO2JH/HWOp5u1Ha 2h4kn6V5AKJV0pnSJDBGUir4TtA9xcDgMLGQoqrJyrKGvnZhcuJvf6oFWsAD4eAy8zFc fK9roHvVG5t6Oimq0X3bY4yMlFzv+L+CP9Vv6Mv9bWtshUJ5BEAMQJeWZVr54RqQZYiE tu6g== X-Received: by 10.66.27.3 with SMTP id p3mr8416151pag.68.1374075385372; Wed, 17 Jul 2013 08:36:25 -0700 (PDT) Received: from localhost (jfdmzpr05-ext.jf.intel.com. [134.134.139.74]) by mx.google.com with ESMTPSA id ys4sm8522707pbb.9.2013.07.17.08.36.23 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 17 Jul 2013 08:36:24 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Wed, 17 Jul 2013 12:36:12 -0300 Message-Id: <1374075372-5648-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 Subject: [Intel-gfx] [PATCH] drm/i915: Extend i915_powersave parameter. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP i915_powersave was already an umbrella for disabling downclocking and fbc. Now on it is extended to also force enabling them. Also more powersavings features has been added under it: RC6 and IPS. In the future it can cover more powersavings features like PSR, Slice Shutdown, etc. So this will be the easiest path to disable or enable all of them together. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.c | 9 +++++++-- drivers/gpu/drm/i915/intel_display.c | 9 +++++---- drivers/gpu/drm/i915/intel_pm.c | 13 ++++++------- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b07362f..e4fb431 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -53,10 +53,15 @@ MODULE_PARM_DESC(panel_ignore_lid, "Override lid status (0=autodetect, 1=autodetect disabled [default], " "-1=force lid closed, -2=force lid open)"); -unsigned int i915_powersave __read_mostly = 1; +unsigned int i915_powersave __read_mostly = -1; module_param_named(powersave, i915_powersave, int, 0600); MODULE_PARM_DESC(powersave, - "Enable powersavings, fbc, downclocking, etc. (default: true)"); + "Force Enable/Disable powersavings," + "ignoring individual parameters when available." + "Features covered: downclocking, fbc, rc6 and ips" + "0 = forcibly disables all powersavings features" + "1 = forcibly enables all powersavings features" + "default: -1 (use per-feature default/parameter)"); int i915_semaphores __read_mostly = -1; module_param_named(semaphores, i915_semaphores, int, 0600); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f53359b..e84a7d9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4089,7 +4089,8 @@ retry: static void hsw_compute_ips_config(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config) { - pipe_config->ips_enabled = i915_enable_ips && + pipe_config->ips_enabled = i915_powersave != 0 && + (i915_powersave == 1 || i915_enable_ips) && hsw_crtc_supports_ips(crtc) && pipe_config->pipe_bpp == 24; } @@ -4329,7 +4330,7 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, crtc->lowfreq_avail = false; if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && - reduced_clock && i915_powersave) { + reduced_clock && i915_powersave == 0) { I915_WRITE(FP1(pipe), fp2); crtc->config.dpll_hw_state.fp1 = fp2; crtc->lowfreq_avail = true; @@ -7156,7 +7157,7 @@ void intel_mark_idle(struct drm_device *dev) { struct drm_crtc *crtc; - if (!i915_powersave) + if (i915_powersave == 0) return; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -7173,7 +7174,7 @@ void intel_mark_fb_busy(struct drm_i915_gem_object *obj, struct drm_device *dev = obj->base.dev; struct drm_crtc *crtc; - if (!i915_powersave) + if (i915_powersave == 0) return; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 43031ec..405b475 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -452,9 +452,6 @@ void intel_update_fbc(struct drm_device *dev) struct drm_i915_gem_object *obj; unsigned int max_hdisplay, max_vdisplay; - if (!i915_powersave) - return; - if (!I915_HAS_FBC(dev)) return; @@ -491,13 +488,13 @@ void intel_update_fbc(struct drm_device *dev) intel_fb = to_intel_framebuffer(fb); obj = intel_fb->obj; - if (i915_enable_fbc < 0 && + if (i915_enable_fbc < 0 && i915_powersave < 0 && INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { DRM_DEBUG_KMS("disabled per chip default\n"); dev_priv->fbc.no_fbc_reason = FBC_CHIP_DEFAULT; goto out_disable; } - if (!i915_enable_fbc) { + if (!i915_enable_fbc || i915_powersave == 0) { DRM_DEBUG_KMS("fbc disabled per module param\n"); dev_priv->fbc.no_fbc_reason = FBC_MODULE_PARAM; goto out_disable; @@ -3171,12 +3168,14 @@ int intel_enable_rc6(const struct drm_device *dev) if (INTEL_INFO(dev)->gen < 5) return 0; - /* Respect the kernel parameter if it is set */ + /* Respect the kernel parameters if they are set */ + if (i915_powersave == 0) + return 0; if (i915_enable_rc6 >= 0) return i915_enable_rc6; /* Disable RC6 on Ironlake */ - if (INTEL_INFO(dev)->gen == 5) + if (INTEL_INFO(dev)->gen == 5 && i915_powersave < 0) return 0; if (IS_HASWELL(dev)) {