From patchwork Fri Aug 16 00:30:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: James Ausmus X-Patchwork-Id: 2845346 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F0C4A9F239 for ; Fri, 16 Aug 2013 00:53:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 203F2202B1 for ; Fri, 16 Aug 2013 00:53:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3277E2021E for ; Fri, 16 Aug 2013 00:53:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B219E84FA for ; Thu, 15 Aug 2013 17:53:26 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id BCEADE665C for ; Thu, 15 Aug 2013 17:32:08 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 15 Aug 2013 17:29:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,889,1367996400"; d="scan'208";a="387901454" Received: from jausmus-gentoo-dev5.jf.intel.com ([10.7.198.60]) by orsmga002.jf.intel.com with ESMTP; 15 Aug 2013 17:31:56 -0700 From: james.ausmus@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Aug 2013 17:30:47 -0700 Message-Id: <1376613069-15790-23-git-send-email-james.ausmus@intel.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1376613069-15790-1-git-send-email-james.ausmus@intel.com> References: <1376613069-15790-1-git-send-email-james.ausmus@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] CHROMIUM: drm/i915: Check the current edp backlight state before changing it. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stéphane Marchesin This speeds up boot and suspend/resume times. BUG=chrome-os-partner:13364 TEST=by hand Change-Id: I8d7b7a22c50bcf32828d492e123ce301cefa297d Reviewed-on: https://gerrit.chromium.org/gerrit/37047 Reviewed-by: Simon Que Commit-Ready: Stéphane Marchesin Tested-by: Stéphane Marchesin --- drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 29013de..f763d45 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1195,6 +1195,10 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp) return; DRM_DEBUG_KMS("\n"); + pp = ironlake_get_pp_control(dev_priv); + if (pp & EDP_BLC_ENABLE) + return; + /* * If we enable the backlight right away following a panel power * on, we may see slight flicker as the panel syncs with the eDP @@ -1202,7 +1206,6 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp) * allowing it to appear. */ msleep(intel_dp->backlight_on_delay); - pp = ironlake_get_pp_control(dev_priv); pp |= EDP_BLC_ENABLE; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); @@ -1223,6 +1226,8 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp) DRM_DEBUG_KMS("\n"); pp = ironlake_get_pp_control(dev_priv); + if (!(pp & EDP_BLC_ENABLE)) + return; pp &= ~EDP_BLC_ENABLE; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL);