From patchwork Fri Aug 16 00:31:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: James Ausmus X-Patchwork-Id: 2845316 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1AED5BF546 for ; Fri, 16 Aug 2013 00:38:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2C5F3202AE for ; Fri, 16 Aug 2013 00:38:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3536B202A1 for ; Fri, 16 Aug 2013 00:38:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 33BAEE64E6 for ; Thu, 15 Aug 2013 17:38:45 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 21BAEE630D for ; Thu, 15 Aug 2013 17:31:59 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 15 Aug 2013 17:31:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,889,1367996400"; d="scan'208";a="387901467" Received: from jausmus-gentoo-dev5.jf.intel.com ([10.7.198.60]) by orsmga002.jf.intel.com with ESMTP; 15 Aug 2013 17:31:57 -0700 From: james.ausmus@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Aug 2013 17:31:00 -0700 Message-Id: <1376613069-15790-36-git-send-email-james.ausmus@intel.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1376613069-15790-1-git-send-email-james.ausmus@intel.com> References: <1376613069-15790-1-git-send-email-james.ausmus@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] CHROMIUM: drm/i915: tune the RC6 timeout for stability X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stéphane Marchesin It's basically the same deal as the RC6+ issues on ivy bridge (https://gerrit.chromium.org/gerrit/#/c/42655/) except this time with RC6 on sandy bridge. Like last time the core of the issue is that the existing timings don't work 100% with our voltage regulator, so once in a couple suspend/resumes the kernel will print a warning message about the GPU not getting out of RC6. Luckily this time the shared timings are already working (from the ivy bridge work) so we only need to adjust the one RC6-specific timing, GEN6_RC6_THRESHOLD. Just like with the RC6+ change, I couldn't see any measurable power difference with an idle lumpy. BUG=chromium:235116 TEST=ran the power_Resume a bunch on stumpy, didn't see an RC6 error TEST=tested lumpy for power regressions on idle Change-Id: I0e1be040e0e156cd38d6c396e237d4a01a16a6a2 Reviewed-on: https://gerrit.chromium.org/gerrit/57868 Reviewed-by: Vincent Palatin Commit-Queue: Stéphane Marchesin Tested-by: Stéphane Marchesin --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1b487cb..8105d10 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2572,7 +2572,7 @@ static void gen6_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_SLEEP, 0); I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); - I915_WRITE(GEN6_RC6_THRESHOLD, 50000); + I915_WRITE(GEN6_RC6_THRESHOLD, 150000); I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */