From patchwork Wed Sep 4 20:26:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2853846 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3DA209F494 for ; Wed, 4 Sep 2013 20:26:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 138E92051C for ; Wed, 4 Sep 2013 20:26:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D51A820515 for ; Wed, 4 Sep 2013 20:26:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 368CDE5D42 for ; Wed, 4 Sep 2013 13:26:49 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qa0-f46.google.com (mail-qa0-f46.google.com [209.85.216.46]) by gabe.freedesktop.org (Postfix) with ESMTP id A787EE5CE2 for ; Wed, 4 Sep 2013 13:26:36 -0700 (PDT) Received: by mail-qa0-f46.google.com with SMTP id i13so2262543qae.5 for ; Wed, 04 Sep 2013 13:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Co42jskz6smJisuzU1fY2r9pwgaisxC6J3D/+gLBH3Q=; b=ZpGeV16cDh05lftapQibGyjNksMPgSb5SJyuV9CeC5R/YS1jFtSR8xcTO/Web7nfDb SG6zTf+PSFdIczOIxlk1jkAPizxw3z6y7L7EOIooHhR1fA7h+1Ok4CgdJkmnUbIazqnx mItSMA4mjsN6p2MD6BIXBlR/kIxGN09ASjFBTtBMr9FG773uBSR1uvgugsaJ6RRX1+Q6 byHKn9r7+EICkFdcm6K66K9AvsD6+ctoeHQXpiwa/5GG1WGrT9C6CN3XYoeHapxod6dI wk/JieWpYkbMkOPCNqFFWeE43VJXMukxgwjLOWycuTPRfXq9HW77qVZh4LbIiFi41Pa5 N5KA== X-Received: by 10.224.92.143 with SMTP id r15mr2928270qam.125.1378326395700; Wed, 04 Sep 2013 13:26:35 -0700 (PDT) Received: from localhost.localdomain ([186.204.164.107]) by mx.google.com with ESMTPSA id fy7sm39759036qeb.1.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 04 Sep 2013 13:26:35 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Wed, 4 Sep 2013 17:26:32 -0300 Message-Id: <1378326393-8193-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Allow GT3 Slice Shutdown on Boot. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Slice shutdown is a power savings feature whereby parts of HW i.e. slice is shut off on boot or dynamically to save power. This patch only introduces a way to disable half of Haswell GT3 slices on boot. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 5 ----- drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++ 5 files changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 72e2be7..2650071 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -154,6 +154,11 @@ module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); MODULE_PARM_DESC(prefault_disable, "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); +int i915_gt3_policy __read_mostly = 1; +module_param_named(gt3_policy, i915_gt3_policy, int, 0600); +MODULE_PARM_DESC(gt3_policy, + "GT3 boot with Full (1) or Half (0) slices enabled. (default:full)"); + static struct drm_driver driver; extern int intel_agp_enabled; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 769c138..b1c148b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1726,6 +1726,7 @@ extern bool i915_fastboot __read_mostly; extern int i915_enable_pc8 __read_mostly; extern int i915_pc8_timeout __read_mostly; extern bool i915_prefault_disable __read_mostly; +extern int i915_gt3_policy __read_mostly; extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_resume(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fdeecae..9b13651 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4335,11 +4335,6 @@ i915_gem_init_hw(struct drm_device *dev) if (dev_priv->ellc_size) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); - if (IS_HSW_GT3(dev)) - I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); - else - I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); - if (HAS_PCH_NOP(dev)) { u32 temp = I915_READ(GEN7_MSG_CTL); temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c7f2da3..c6dd502 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -269,6 +269,17 @@ #define LOWER_SLICE_ENABLED (1<<0) #define LOWER_SLICE_DISABLED (0<<0) +#define HSW_GT_SLICE_INFO 0x138064 +#define SLICE_SEL_BOTH (1<<3) +#define SLICE_AUTOWAKE (1<<2) +#define SLICE_STATUS_MASK 0x3 +#define SLICE_STATUS_GT_OFF (0<<0) +#define SLICE_STATUS_MAIN_ON (2<<0) +#define SLICE_STATUS_BOTH_ON (3<<0) + +#define HSW_SLICESHUTDOWN 0xA190 +#define SLICE_SHUTDOWN (1<<0) + /* * 3D instructions used by the kernel */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0c115cc..5b58eee 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3617,6 +3617,28 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } +static void intel_init_gt3_slices(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_HSW_GT3(dev)) + return; + + if (!i915_gt3_policy) { + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); + + I915_WRITE(HSW_SLICESHUTDOWN, SLICE_SHUTDOWN); + POSTING_READ(HSW_SLICESHUTDOWN); + + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + POSTING_READ(HSW_GT_SLICE_INFO); + } else { + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); + } +} + void gen6_update_ring_freq(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4630,6 +4652,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) } else { gen6_enable_rps(dev); gen6_update_ring_freq(dev); + intel_init_gt3_slices(dev); } mutex_unlock(&dev_priv->rps.hw_lock); }