From patchwork Tue Sep 10 22:36:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2868211 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BF3CEBF43F for ; Tue, 10 Sep 2013 23:17:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DC2CE203DA for ; Tue, 10 Sep 2013 23:17:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0353C20357 for ; Tue, 10 Sep 2013 23:17:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 075EFE640F for ; Tue, 10 Sep 2013 16:17:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f46.google.com (mail-yh0-f46.google.com [209.85.213.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 7716BE7713 for ; Tue, 10 Sep 2013 15:37:34 -0700 (PDT) Received: by mail-yh0-f46.google.com with SMTP id c41so2919461yho.5 for ; Tue, 10 Sep 2013 15:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S660ezQSeLji46i2cu1ta8JXfCERl0UrISbhsMcv7n0=; b=pEbKuQNTtWP7/78iuErOud7ezHt7iSkoXn6r9nAiJXwsR9z8V1SYf5i+nb/8TmEDvp GreXyolgiXPxPvPHAeSe9DWZ3cdF0gWc/CeV2NXNWmZOh1j2+b5G8RzeRdb/vR7822Bh pF2cePDA3upVbfWz0fugUX0U1uk3WvCwymBAi9iIw7PhkzOCRmnWua7Ywn+LQDQPs6AE I44R22OTiv5toXOhH4Q8YbnBSLBl9Ll6UbP1I7FHdKjUvVFR5nSLpbv55odqJb+J2eq1 kXLFWV5xNFclETMmHiQNTHp9e8zSpnmflLbMhLaCH45jY11wqk0Y7MkB87sLKJG+Digl d62w== X-Received: by 10.236.156.5 with SMTP id l5mr23906251yhk.5.1378852653701; Tue, 10 Sep 2013 15:37:33 -0700 (PDT) Received: from localhost.localdomain ([186.204.164.107]) by mx.google.com with ESMTPSA id v22sm27925176yhn.12.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 10 Sep 2013 15:37:33 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Sep 2013 19:36:48 -0300 Message-Id: <1378852608-30281-20-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1378852608-30281-1-git-send-email-rodrigo.vivi@gmail.com> References: <1378852608-30281-1-git-send-email-rodrigo.vivi@gmail.com> Subject: [Intel-gfx] [PATCH 19/19] drm/i915: Allow Dynamically GT3 Slice Shutdown. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Slice shutdown is a power savings feature whereby parts of HW i.e. slice is shut off on boot or dynamically to save power. This patch introduces a sysfs interface to easily allow dynamically switch between full and half GT3 slices. v2: remove unused variables and fix identation Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_sysfs.c | 48 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 4 +++- drivers/gpu/drm/i915/intel_pm.c | 31 +++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 491aba6..a87c260 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -93,6 +93,48 @@ static struct attribute_group rc6_attr_group = { .name = power_group_name, .attrs = rc6_attrs }; + +static ssize_t gt3_policy_show(struct device *kdev, + struct device_attribute *attr, char *buf) +{ + struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev); + struct drm_device *dev = minor->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + return sprintf(buf, "%s\n", I915_READ(MI_PREDICATE_RESULT_2) == + LOWER_SLICE_ENABLED ? "full" : "half"); +} + +static ssize_t gt3_policy_store(struct device *kdev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev); + struct drm_device *dev = minor->dev; + + if (!strncmp(buf, "full", sizeof("full") - 1)) + intel_set_gt3_full(dev); + else if (!strncmp(buf, "half", sizeof("half") - 1)) + intel_set_gt3_half(dev); + else + return -EINVAL; + + return count; +} + +static DEVICE_ATTR(gt3_policy, S_IRUGO | S_IWUSR, + gt3_policy_show, gt3_policy_store); + +static struct attribute *gt3_policy_attrs[] = { + &dev_attr_gt3_policy.attr, + NULL +}; + +static struct attribute_group gt3_policy_attr_group = { + .name = power_group_name, + .attrs = gt3_policy_attrs +}; + #endif static int l3_access_valid(struct drm_device *dev, loff_t offset) @@ -518,6 +560,12 @@ void i915_setup_sysfs(struct drm_device *dev) if (ret) DRM_ERROR("RC6 residency sysfs setup failed\n"); } + if (IS_HSW_GT3(dev)) { + ret = sysfs_merge_group(&dev->primary->kdev.kobj, + >3_policy_attr_group); + if (ret) + DRM_ERROR("GT3 policy sysfs setup failed\n"); + } #endif if (HAS_L3_GPU_CACHE(dev)) { ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c6807d7..ced31f1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -739,7 +739,9 @@ extern void intel_update_fbc(struct drm_device *dev); /* IPS */ extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); extern void intel_gpu_ips_teardown(void); - +/* Slice Shutdown */ +extern void intel_set_gt3_full(struct drm_device *dev); +extern void intel_set_gt3_half(struct drm_device *dev); /* Power well */ extern int i915_init_power_well(struct drm_device *dev); extern void i915_remove_power_well(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2b9db88..a87be43 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3697,6 +3697,37 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } +void intel_set_gt3_full(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_HSW_GT3(dev)) + return; + + I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH); + POSTING_READ(HSW_GT_SLICE_INFO); + + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); +} + +void intel_set_gt3_half(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_HSW_GT3(dev)) + return; + + I915_WRITE(HSW_SLICESHUTDOWN, SLICE_SHUTDOWN); + POSTING_READ(HSW_SLICESHUTDOWN); + + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + POSTING_READ(HSW_GT_SLICE_INFO); + + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); +} + static void intel_init_gt3_slices(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private;