From patchwork Tue Oct 15 14:41:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 3047301 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9D9F19F243 for ; Tue, 15 Oct 2013 18:29:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7865C20306 for ; Tue, 15 Oct 2013 18:29:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 631E120295 for ; Tue, 15 Oct 2013 18:29:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4DD74E60B8 for ; Tue, 15 Oct 2013 11:29:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ve0-f182.google.com (mail-ve0-f182.google.com [209.85.128.182]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A5DFE8AE8 for ; Tue, 15 Oct 2013 07:31:38 -0700 (PDT) Received: by mail-ve0-f182.google.com with SMTP id jx11so694817veb.41 for ; Tue, 15 Oct 2013 07:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xSnu12oVGeV9W2GqGuV7gdFUQil6d4TuYTv7ZR0Qj2o=; b=wEOL0qBQs50xkyE+3takJGcKqt6BDRX2raXz225DscGjfRF4P0DOAeeG9OUR+jlu8l AYJoZhPtlCwEhcWf2zOYvP4MTqWg26LhtVfpCc4D2zWA+gNED43yOVpiHxbUMADEy/SN 6J4XWChiOPLclzszF/apedsTl2HuE3WcaEdufqzdfLN8VIJTyh+ixl6ySfzWQWm3eikY OSKzYjnmC6gf69Ux88RXxZo0q1oS5NC3urlqBMOUK0ap/nQUKWqDw9GwBmQHa+RCAv+a JogIWft6w8ptHmy1g+Jvyn/tmGxw/TLTjHlEwb+CQtorptpR3NN1/EQE9ePNVOXcD0vf Ibbw== X-Received: by 10.52.65.136 with SMTP id x8mr1524307vds.23.1381847497769; Tue, 15 Oct 2013 07:31:37 -0700 (PDT) Received: from localhost.localdomain ([189.40.73.246]) by mx.google.com with ESMTPSA id gr8sm88324803vdc.10.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 15 Oct 2013 07:31:37 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 15 Oct 2013 11:41:06 -0300 Message-Id: <1381848067-5269-4-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1381848067-5269-1-git-send-email-rodrigo.vivi@gmail.com> References: <1381848067-5269-1-git-send-email-rodrigo.vivi@gmail.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Slice Shutdown: Allow setting slice config (full x half) through sysfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch introduces a sysfs interface to easily allow dynamically switch slice config default behaviour between full and half slices. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_sysfs.c | 54 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++++++++++++++++++++++++++++++-- 4 files changed, 112 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 02d82d8..685fb1d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1728,6 +1728,7 @@ struct drm_i915_file_private { #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_PSR(dev) (IS_HASWELL(dev)) +#define HAS_SLICE_SHUTDOWN(dev) (IS_HSW_GT3(dev) && i915_enable_rc6) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index bb31ff3..86ccd52 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -117,6 +117,52 @@ static struct attribute_group rc6_attr_group = { .name = power_group_name, .attrs = rc6_attrs }; + +static ssize_t gt_slice_config_show(struct device *kdev, + struct device_attribute *attr, char *buf) +{ + struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev); + struct drm_device *dev = minor->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + return sprintf(buf, "%s\n", I915_READ(MI_PREDICATE_RESULT_2) == + LOWER_SLICE_ENABLED ? "full" : "half"); +} + +static ssize_t gt_slice_config_store(struct device *kdev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev); + struct drm_device *dev = minor->dev; + int ret; + + if (!strncmp(buf, "full", sizeof("full") - 1)) { + ret = intel_set_gt_full(dev); + if (ret) + return ret; + } else if (!strncmp(buf, "half", sizeof("half") - 1)) { + ret = intel_set_gt_half(dev); + if (ret) + return ret; + } else + return -EINVAL; + return count; +} + +static DEVICE_ATTR(gt_slice_config, S_IRUGO | S_IWUSR, gt_slice_config_show, + gt_slice_config_store); + +static struct attribute *gt_slice_config_attrs[] = { + &dev_attr_gt_slice_config.attr, + NULL +}; + +static struct attribute_group gt_slice_config_attr_group = { + .name = power_group_name, + .attrs = gt_slice_config_attrs +}; + #endif static int l3_access_valid(struct drm_device *dev, loff_t offset) @@ -558,6 +604,12 @@ void i915_setup_sysfs(struct drm_device *dev) if (ret) DRM_ERROR("RC6 residency sysfs setup failed\n"); } + if (HAS_SLICE_SHUTDOWN(dev)) { + ret = sysfs_merge_group(&dev->primary->kdev.kobj, + >_slice_config_attr_group); + if (ret) + DRM_ERROR("GT slice config sysfs setup failed\n"); + } #endif if (HAS_L3_DPF(dev)) { ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs); @@ -597,5 +649,7 @@ void i915_teardown_sysfs(struct drm_device *dev) device_remove_bin_file(&dev->primary->kdev, &dpf_attrs); #ifdef CONFIG_PM sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group); + sysfs_unmerge_group(&dev->primary->kdev.kobj, + >_slice_config_attr_group); #endif } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f21f3fa..a9abbb5 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -834,6 +834,8 @@ void intel_set_power_well(struct drm_device *dev, bool enable); void intel_enable_gt_powersave(struct drm_device *dev); void intel_disable_gt_powersave(struct drm_device *dev); void ironlake_teardown_rc6(struct drm_device *dev); +int intel_set_gt_full(struct drm_device *dev); +int intel_set_gt_half(struct drm_device *dev); void intel_init_gt_slices(struct drm_device *dev); void gen6_update_ring_freq(struct drm_device *dev); void gen6_rps_idle(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a1a2588..63af075 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3866,14 +3866,66 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } -void intel_init_gt_slices(struct drm_device *dev) +int intel_set_gt_full(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (!IS_HSW_GT3(dev)) - return; + if (!HAS_SLICE_SHUTDOWN(dev)) + return -ENODEV; + + I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH); + + /* Slices are enabled on RC6 exit */ + gen6_gt_force_wake_get(dev_priv); + if (wait_for(((I915_READ(HSW_GT_SLICE_INFO) & SLICE_STATUS_MASK) == + SLICE_STATUS_BOTH_ON), 2000)) { + DRM_ERROR("Timeout enabling full gt slices\n"); + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + gen6_gt_force_wake_put(dev_priv); + return -ETIMEDOUT; + } I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + gen6_gt_force_wake_put(dev_priv); + + return 0; +} + +int intel_set_gt_half(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!HAS_SLICE_SHUTDOWN(dev)) + return -ENODEV; + + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + + /* Slices are disabled on RC6 exit */ + gen6_gt_force_wake_get(dev_priv); + + if (wait_for(((I915_READ(HSW_GT_SLICE_INFO) & SLICE_STATUS_MASK) == + SLICE_STATUS_MAIN_ON), 2000)) { + DRM_ERROR("Timed out disabling half gt slices\n"); + I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH); + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + gen6_gt_force_wake_put(dev_priv); + return -ETIMEDOUT; + } + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + gen6_gt_force_wake_put(dev_priv); + return 0; +} + +void intel_init_gt_slices(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (IS_HSW_GT3(dev)) + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + + if (!HAS_SLICE_SHUTDOWN(dev)) + return; if (!i915_gt_slice_config) { I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH);