From patchwork Thu Oct 24 16:59:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3092901 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 141C8BF924 for ; Thu, 24 Oct 2013 17:37:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4A40F204A2 for ; Thu, 24 Oct 2013 17:37:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 34100204AF for ; Thu, 24 Oct 2013 17:37:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10D95E661D for ; Thu, 24 Oct 2013 10:37:31 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 19AAAE63E9 for ; Thu, 24 Oct 2013 09:59:27 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 24 Oct 2013 09:59:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,535,1378882800"; d="scan'208";a="398117650" Received: from lundgren.jf.intel.com ([10.7.197.63]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2013 09:59:18 -0700 From: Ben Widawsky To: Intel GFX Date: Thu, 24 Oct 2013 09:59:13 -0700 Message-Id: <1382633954-7375-3-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.4.1 In-Reply-To: <1382633954-7375-1-git-send-email-benjamin.widawsky@intel.com> References: <1382633954-7375-1-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky , Art Runyan , Ben Widawsky Subject: [Intel-gfx] [PATCH 3/4] drm/i915: WaFbcDisableDpfcrClockGating only with fbc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We were turning this on for ILK regardless of whether or not we use FBC. We can save the slightest amount of power if we don't disable it when not using FBC. The workaround should be bit 8 for ILK. Notice it is 1 bit difference from SNB. This is actually DPFCR unit as we've defined it. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 686699c..bbcf100 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -238,6 +238,11 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) SNB_CPU_FENCE_ENABLE | obj->fence_reg); I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); sandybridge_blit_fbc_update(dev); + } else { + /* WaFbcDisableDpfcClockGating:ilk */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) | + ILK_DPFCRUNIT_CLOCK_GATE_DISABLE); } DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); @@ -254,6 +259,12 @@ static void ironlake_disable_fbc(struct drm_device *dev) dpfc_ctl &= ~DPFC_CTL_EN; I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); + if (IS_GEN5(dev)) + /* WaFbcDisableDpfcClockGating:ilk */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) & + ~ILK_DPFCRUNIT_CLOCK_GATE_DISABLE); + DRM_DEBUG_KMS("disabled FBC\n"); } } @@ -4932,9 +4943,9 @@ static void ironlake_init_clock_gating(struct drm_device *dev) /* * Required for FBC - * WaFbcDisableDpfcClockGating:ilk + * WaFbcDisableDpfcClockGating:snb */ - dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | + dspclk_gate |= ILK_DPFCUNIT_CLOCK_GATE_DISABLE | ILK_DPFDUNIT_CLOCK_GATE_ENABLE;