From patchwork Tue Nov 5 22:44:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 3144111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 86B379F432 for ; Tue, 5 Nov 2013 22:44:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8A08E2047D for ; Tue, 5 Nov 2013 22:44:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A185C2041B for ; Tue, 5 Nov 2013 22:44:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56E93FB869; Tue, 5 Nov 2013 14:44:37 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qa0-f51.google.com (mail-qa0-f51.google.com [209.85.216.51]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FC45FB866 for ; Tue, 5 Nov 2013 14:44:33 -0800 (PST) Received: by mail-qa0-f51.google.com with SMTP id hu16so1350660qab.17 for ; Tue, 05 Nov 2013 14:44:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OpDJgWybKK1oKEiayVNMC3VdxtZwcGRqS6+vATX6B20=; b=UyXaJaK4w4Y9rSZamzvvWWgUG7t43Q99nR6jvQ4kOTZ9tMwZqlqMp8hZ2f9NSiQr/r EXZ2f3f9FSo9ktS/8UzxEp1S4w1zDa0SzcKM0nwyidOtpFrQHpHPDgm2M4L7dP01SxjY q0usHuW9ml+V/EbuRupc4c0ARH7sSJHzs5HiNj9ABUOdE33qGoXv8ToekmqhEzjQiseA lUIF/w17UPMcJiAhTHe42Z4KX9LAQMNMME7mp8Z53fl3Vd8upoMBSJ3O61fw8bkNcKmn vAp/M4SBZgciuqxOvrPhoSydXRk8Y9XLDK4mYENdG1V+0sekN18hkQrqMd0wXF0Bi0GC V5QA== X-Received: by 10.49.50.198 with SMTP id e6mr13969264qeo.87.1383691473101; Tue, 05 Nov 2013 14:44:33 -0800 (PST) Received: from localhost.localdomain ([177.140.135.10]) by mx.google.com with ESMTPSA id 48sm39881760yhq.11.2013.11.05.14.44.31 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Nov 2013 14:44:32 -0800 (PST) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Nov 2013 20:44:13 -0200 Message-Id: <1383691456-2564-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1381848067-5269-1-git-send-email-rodrigo.vivi@gmail.com> References: <1381848067-5269-1-git-send-email-rodrigo.vivi@gmail.com> Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Allow GT Slices Shutdown on Boot. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Slices shutdown is a power savings feature present on Haswell GT3 whereby parts of HW i.e. slice is shut off on boot or dynamically to save power. This patch only introduces a way to disable half of Haswell GT3 slices on boot. v2: Use number of slices on (1 or 2) instead of 0 for half and 1 for full. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 5 +---- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++++++- 6 files changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a0804fa..71bac6a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -154,6 +154,11 @@ module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); MODULE_PARM_DESC(prefault_disable, "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); +int i915_gt_slices __read_mostly = 2; +module_param_named(gt_slices, i915_gt_slices, int, 0600); +MODULE_PARM_DESC(gt_slices, + "Haswell GT3 has two slices with many EUs in each of them. Use 2 for better performance or 1 for better power savings. (default:2)"); + static struct drm_driver driver; extern int intel_agp_enabled; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b12d942..27073e8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1836,6 +1836,7 @@ extern bool i915_fastboot __read_mostly; extern int i915_enable_pc8 __read_mostly; extern int i915_pc8_timeout __read_mostly; extern bool i915_prefault_disable __read_mostly; +extern int i915_gt_slices __read_mostly; extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_resume(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e7b39d7..f9c32d1 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4439,10 +4439,7 @@ i915_gem_init_hw(struct drm_device *dev) if (dev_priv->ellc_size) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); - if (IS_HSW_GT3(dev)) - I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); - else - I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + intel_init_gt_slices(dev); if (HAS_PCH_NOP(dev)) { u32 temp = I915_READ(GEN7_MSG_CTL); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3f303ba..a2e7deb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -270,6 +270,14 @@ #define LOWER_SLICE_ENABLED (1<<0) #define LOWER_SLICE_DISABLED (0<<0) +#define HSW_GT_SLICE_INFO 0x138064 +#define SLICE_SEL_BOTH (1<<3) +#define SLICE_AUTOWAKE (1<<2) +#define SLICE_STATUS_MASK 0x3 +#define SLICE_STATUS_GT_OFF (0<<0) +#define SLICE_STATUS_MAIN_ON (2<<0) +#define SLICE_STATUS_BOTH_ON (3<<0) + /* * 3D instructions used by the kernel */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9d2624f..42c3983 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -836,6 +836,7 @@ void intel_set_power_well(struct drm_device *dev, bool enable); void intel_enable_gt_powersave(struct drm_device *dev); void intel_disable_gt_powersave(struct drm_device *dev); void ironlake_teardown_rc6(struct drm_device *dev); +void intel_init_gt_slices(struct drm_device *dev); void gen6_update_ring_freq(struct drm_device *dev); void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 09ac9e7..02d1b1f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3869,6 +3869,25 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } +void intel_init_gt_slices(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_HSW_GT3(dev)) + return; + + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + + if (i915_gt_slices == 1) { + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + return; + } + + if (i915_gt_slices != 2) + DRM_ERROR("Invalid number of slices. 2 GT slices enabled\n"); +} + void gen6_update_ring_freq(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -5995,4 +6014,3 @@ void intel_pm_init(struct drm_device *dev) INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); } -