From patchwork Fri Nov 15 18:41:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Romanick X-Patchwork-Id: 3189461 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2E61CC045B for ; Fri, 15 Nov 2013 18:42:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DEDE208A5 for ; Fri, 15 Nov 2013 18:42:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1BB99207BD for ; Fri, 15 Nov 2013 18:42:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4BD3FAF93; Fri, 15 Nov 2013 10:42:10 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from expn.cat.pdx.edu (expn.cat.pdx.edu [131.252.208.110]) by gabe.freedesktop.org (Postfix) with ESMTP id E94D3FA463; Fri, 15 Nov 2013 10:42:07 -0800 (PST) Received: from idr ([127.0.0.1])(authenticated bits=0) by expn.cat.pdx.edu (8.14.4/8.14.4/Debian-2ubuntu2) with ESMTP id rAFIg26i025859 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 15 Nov 2013 10:42:06 -0800 From: "Ian Romanick" To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 15 Nov 2013 10:41:57 -0800 Message-Id: <1384540917-7099-1-git-send-email-idr@freedesktop.org> X-Mailer: git-send-email 1.8.1.4 X-Virus-Scanned: clamav-milter 0.97.8 at expn X-Virus-Status: Clean Cc: Daniel Vetter , Ian Romanick , Mika Kuoppala Subject: [Intel-gfx] [PATCH] intel: Add support for GPU reset status query ioctl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ian Romanick I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. This ioctl is in the drm-intel-next tree as b635991. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. v4: Import the actual changes from the kernel i915_drm.h. Only comments on some fields of drm_i915_reset_stats differed. There are still some deltas between the kernel i915_drm.h and the one in libdrm, but those can be resolved in other patches. Signed-off-by: Ian Romanick Reviewed-by: Kenneth Graunke [v3] Cc: Mika Kuoppala Cc: Daniel Vetter Reviewed-by: Damien Lespiau --- include/drm/i915_drm.h | 19 +++++++++++++++++++ intel/intel_bufmgr.h | 5 +++++ intel/intel_bufmgr_gem.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index aa983f3..c1914d6 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -198,6 +198,7 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_SET_CACHEING 0x2f #define DRM_I915_GEM_GET_CACHEING 0x30 #define DRM_I915_REG_READ 0x31 +#define DRM_I915_GET_RESET_STATS 0x32 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -247,6 +248,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) +#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -943,4 +945,21 @@ struct drm_i915_reg_read { __u64 offset; __u64 val; /* Return value */ }; + +struct drm_i915_reset_stats { + __u32 ctx_id; + __u32 flags; + + /* All resets since boot/module reload, for all contexts */ + __u32 reset_count; + + /* Number of batches lost when active in GPU, for this context */ + __u32 batch_active; + + /* Number of batches lost pending for execution, for this context */ + __u32 batch_pending; + + __u32 pad; +}; + #endif /* _I915_DRM_H_ */ diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 7b28a70..34a5750 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -249,6 +249,11 @@ int drm_intel_reg_read(drm_intel_bufmgr *bufmgr, uint32_t offset, uint64_t *result); +int drm_intel_get_reset_stats(drm_intel_context *ctx, + uint32_t *reset_count, + uint32_t *active, + uint32_t *pending); + /** @{ Compatibility defines to keep old code building despite the symbol rename * from dri_* to drm_intel_* */ diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index dbadc52..0b9252e 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3029,6 +3029,40 @@ drm_intel_gem_context_get_hw_context_id(const drm_intel_context *ctx) } int +drm_intel_get_reset_stats(drm_intel_context *ctx, + uint32_t *reset_count, + uint32_t *active, + uint32_t *pending) +{ + drm_intel_bufmgr_gem *bufmgr_gem; + struct drm_i915_reset_stats stats; + int ret; + + if (ctx == NULL) + return -EINVAL; + + VG_CLEAR(stats); + + bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr; + stats.ctx_id = ctx->ctx_id; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GET_RESET_STATS, + &stats); + if (ret == 0) { + if (reset_count != NULL) + *reset_count = stats.reset_count; + + if (active != NULL) + *active = stats.batch_active; + + if (pending != NULL) + *pending = stats.batch_pending; + } + + return ret; +} + +int drm_intel_reg_read(drm_intel_bufmgr *bufmgr, uint32_t offset, uint64_t *result)