diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7619eae..46f202b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3481,6 +3481,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	struct drm_display_mode *scan;
 	struct edid *edid;
 
+	intel_dp->drrs_state.is_drrs_supported = DRRS_NOT_SUPPORTED;
 	if (!is_edp(intel_dp))
 		return true;
 
@@ -3529,6 +3530,15 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 		}
 	}
 
+	/**
+	 * Do the eDP DRRS support check here as we have valid EDID.
+	 * Parse the list of probed modes and find out if we can get
+	 * a mode with low refresh rate for resolution same as fixed_mode.
+	 */
+	if (fixed_mode && INTEL_INFO(dev)->gen >= 5)
+		intel_dp_find_drrs_lowclk(intel_dig_port,
+					intel_connector, fixed_mode);
+
 	/* fallback to VBT if available for eDP */
 	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
 		fixed_mode = drm_mode_duplicate(dev,
@@ -3738,3 +3748,84 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		kfree(intel_connector);
 	}
 }
+
+static void
+intel_dp_drrs_modelist_create(struct intel_digital_port *intel_dig_port,
+				struct drm_display_mode *fixed_mode,
+				struct drm_display_mode *lowest_mode)
+{
+	struct intel_dp *intel_dp = &intel_dig_port->dp;
+
+	intel_dp->drrs_state.refresh_rate_array[DRRS_HIGH_RR] =
+							fixed_mode->vrefresh;
+	intel_dp->drrs_state.pixel_clock[DRRS_HIGH_RR] = fixed_mode->clock;
+
+	intel_dp->drrs_state.refresh_rate_array[DRRS_LOW_RR] =
+							lowest_mode->vrefresh;
+	intel_dp->drrs_state.pixel_clock[DRRS_LOW_RR] = lowest_mode->clock;
+}
+
+void
+intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
+			     struct intel_connector *intel_connector,
+			     struct drm_display_mode *fixed_mode)
+{
+	struct drm_connector *connector = &intel_connector->base;
+	struct intel_dp *intel_dp = &intel_dig_port->dp;
+	struct intel_encoder *intel_encoder = &intel_dig_port->base;
+	struct drm_device *dev = intel_encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_display_mode *scan, *temp_mode;
+	int downclock;
+
+	intel_dp->drrs_state.is_drrs_supported = DRRS_NOT_SUPPORTED;
+	/**
+	 * Check if PSR is supported by panel and enabled
+	 * if so then DRRS is reported as not supported for Haswell.
+	 */
+
+	if (INTEL_INFO(dev)->gen < 8 &&	intel_edp_is_psr_enabled(dev)) {
+		DRM_INFO("eDP panel is PSR enabled. Cannot support DRRS.\n");
+		return;
+	}
+
+	/* First check if DRRS is enabled from VBT struct */
+	if (!dev_priv->vbt.intel_drrs_enabled) {
+		DRM_INFO("VBT doesn't support DRRS.\n");
+		return;
+	}
+
+	/* Iterate the EDID probed_modes to get the Lowest refresh rate */
+	downclock = fixed_mode->clock;
+	temp_mode = fixed_mode;
+
+	list_for_each_entry(scan, &connector->probed_modes, head) {
+		if (scan->hdisplay == fixed_mode->hdisplay &&
+		    scan->hsync_start == fixed_mode->hsync_start &&
+		    scan->hsync_end == fixed_mode->hsync_end &&
+		    scan->htotal == fixed_mode->htotal &&
+		    scan->vdisplay == fixed_mode->vdisplay &&
+		    scan->vsync_start == fixed_mode->vsync_start &&
+		    scan->vsync_end == fixed_mode->vsync_end &&
+		    scan->vtotal == fixed_mode->vtotal) {
+			if (scan->clock < downclock) {
+				downclock = scan->clock;
+				temp_mode = scan;
+			}
+		}
+	}
+
+	/* Create a list of different DRRS Refresh rates for use later */
+	if (downclock < fixed_mode->clock &&
+	    dev_priv->vbt.drrs_mode == SEAMLESS_DRRS_SUPPORT) {
+		intel_dp_drrs_modelist_create(intel_dig_port, fixed_mode,
+						temp_mode);
+		intel_dp->drrs_state.is_drrs_supported =
+					dev_priv->vbt.drrs_mode;
+		intel_dp->drrs_state.drrs_refresh_rate_type = DRRS_HIGH_RR;
+		DRM_INFO("SEAMLESS DRRS supported for eDP panel.\n");
+	}
+
+	return;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d2624f..bd7964d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -450,6 +450,36 @@ struct intel_hdmi {
 
 #define DP_MAX_DOWNSTREAM_PORTS		0x10
 
+/**
+ * This enum is used to indicate the DRRS support type.
+ * The values of the enum map 1-to-1 with the values from VBT.
+ */
+enum edp_panel_type {
+	DRRS_NOT_SUPPORTED = -1,
+	STATIC_DRRS_SUPPORT = 0,
+	SEAMLESS_DRRS_SUPPORT = 2
+};
+/**
+ * HIGH_RR is the highest eDP panel refresh rate read from EDID
+ * LOW_RR is the lowest eDP panel refresh rate found from EDID
+ * parsing for same resolution.
+ */
+enum edp_drrs_refresh_rate_type {
+	DRRS_HIGH_RR,
+	DRRS_LOW_RR,
+	DRRS_MAX_RR, /* RR count */
+};
+/**
+ * The drrs_info struct will represent the DRRS feature for eDP
+ * panel.
+ */
+struct drrs_info {
+	int is_drrs_supported;
+	int drrs_refresh_rate_type;
+	int refresh_rate_array[DRRS_MAX_RR];
+	int pixel_clock[DRRS_MAX_RR];
+};
+
 struct intel_dp {
 	uint32_t output_reg;
 	uint32_t aux_ch_ctl_reg;
@@ -475,6 +505,7 @@ struct intel_dp {
 	bool want_panel_vdd;
 	bool psr_setup_done;
 	struct intel_connector *attached_connector;
+	struct drrs_info drrs_state;
 };
 
 struct intel_digital_port {
@@ -789,6 +820,10 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
 int intel_overlay_attrs(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 
+/* drrs */
+extern void intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
+				      struct intel_connector *intel_connector,
+				      struct drm_display_mode *fixed_mode);
 
 /* intel_panel.c */
 int intel_panel_init(struct intel_panel *panel,
