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[RFC,17/22] drm/i915: Add parser data for perf monitoring GL extensions

Message ID 1385484699-51596-18-git-send-email-bradley.d.volkin@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

bradley.d.volkin@intel.com Nov. 26, 2013, 4:51 p.m. UTC 
From: Brad Volkin <bradley.d.volkin@intel.com>

These registers and commands will be used by mesa for the
GL_AMD_performance_monitor extension.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h        | 13 +++++++++++++
 2 files changed, 40 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 3ad2a1e..c8426af 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -104,6 +104,13 @@  static const struct drm_i915_cmd_descriptor render_cmds[] = {
 			.expected = 0
 	      }},
 	      .bits_count = 1                                          ),
+	CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
+	      .bits = {{
+			.offset = 1,
+			.mask = MI_REPORT_PERF_COUNT_GGTT,
+			.expected = 0
+	      }},
+	      .bits_count = 1                                          ),
 	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 	      .bits = {{
 			.offset = 0,
@@ -303,8 +310,28 @@  static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
  */
 
 static const u32 gen7_render_regs[] = {
+	HS_INVOCATION_COUNT,
+	HS_INVOCATION_COUNT + sizeof(u32),
+	DS_INVOCATION_COUNT,
+	DS_INVOCATION_COUNT + sizeof(u32),
+	IA_VERTICES_COUNT,
+	IA_VERTICES_COUNT + sizeof(u32),
+	IA_PRIMITIVES_COUNT,
+	IA_PRIMITIVES_COUNT + sizeof(u32),
+	VS_INVOCATION_COUNT,
+	VS_INVOCATION_COUNT + sizeof(u32),
+	GS_INVOCATION_COUNT,
+	GS_INVOCATION_COUNT + sizeof(u32),
+	GS_PRIMITIVES_COUNT,
+	GS_PRIMITIVES_COUNT + sizeof(u32),
 	CL_INVOCATION_COUNT,
 	CL_INVOCATION_COUNT + sizeof(u32),
+	CL_PRIMITIVES_COUNT,
+	CL_PRIMITIVES_COUNT + sizeof(u32),
+	PS_INVOCATION_COUNT,
+	PS_INVOCATION_COUNT + sizeof(u32),
+	PS_DEPTH_COUNT,
+	PS_DEPTH_COUNT + sizeof(u32),
 	GEN7_SO_NUM_PRIMS_WRITTEN(0),
 	GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32),
 	GEN7_SO_NUM_PRIMS_WRITTEN(1),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 232ad0c..4dd5541 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -356,6 +356,8 @@ 
 #define MI_MATH                 MI_INSTR(0x1A, 0)
 #define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
 #define MI_CLFLUSH              MI_INSTR(0x27, 0)
+#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
+#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
 #define MI_LOAD_REGISTER_MEM    MI_INSTR(0x29, 0)
 #define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
 #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
@@ -385,7 +387,18 @@ 
  */
 #define BCS_SWCTRL 0x22200
 
+#define HS_INVOCATION_COUNT 0x2300
+#define DS_INVOCATION_COUNT 0x2308
+#define IA_VERTICES_COUNT   0x2310
+#define IA_PRIMITIVES_COUNT 0x2318
+#define VS_INVOCATION_COUNT 0x2320
+#define GS_INVOCATION_COUNT 0x2328
+#define GS_PRIMITIVES_COUNT 0x2330
 #define CL_INVOCATION_COUNT 0x2338
+#define CL_PRIMITIVES_COUNT 0x2340
+#define PS_INVOCATION_COUNT 0x2348
+#define PS_DEPTH_COUNT      0x2350
+
 /* There are the 4 64-bit counter registers, one for each stream output */
 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)