From patchwork Tue Nov 26 16:51:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bradley.d.volkin@intel.com X-Patchwork-Id: 3239831 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DA220C0C5E for ; Tue, 26 Nov 2013 16:53:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BF0A120416 for ; Tue, 26 Nov 2013 16:53:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8C1E5203F3 for ; Tue, 26 Nov 2013 16:53:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1E9510577F; Tue, 26 Nov 2013 08:53:25 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BA27FB850 for ; Tue, 26 Nov 2013 08:52:26 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 26 Nov 2013 08:52:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,775,1378882800"; d="scan'208";a="415344922" Received: from bdvolkin-desk1.amr.corp.intel.com (HELO localhost.localdomain) ([10.10.34.110]) by orsmga001.jf.intel.com with ESMTP; 26 Nov 2013 08:52:24 -0800 From: bradley.d.volkin@intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 26 Nov 2013 08:51:34 -0800 Message-Id: <1385484699-51596-18-git-send-email-bradley.d.volkin@intel.com> X-Mailer: git-send-email 1.8.4.4 In-Reply-To: <1385484699-51596-1-git-send-email-bradley.d.volkin@intel.com> References: <1385484699-51596-1-git-send-email-bradley.d.volkin@intel.com> Subject: [Intel-gfx] [RFC 17/22] drm/i915: Add parser data for perf monitoring GL extensions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Brad Volkin These registers and commands will be used by mesa for the GL_AMD_performance_monitor extension. Signed-off-by: Brad Volkin --- drivers/gpu/drm/i915/i915_cmd_parser.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 3ad2a1e..c8426af 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -104,6 +104,13 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = { .expected = 0 }}, .bits_count = 1 ), + CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, + .bits = {{ + .offset = 1, + .mask = MI_REPORT_PERF_COUNT_GGTT, + .expected = 0 + }}, + .bits_count = 1 ), CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, .bits = {{ .offset = 0, @@ -303,8 +310,28 @@ static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { */ static const u32 gen7_render_regs[] = { + HS_INVOCATION_COUNT, + HS_INVOCATION_COUNT + sizeof(u32), + DS_INVOCATION_COUNT, + DS_INVOCATION_COUNT + sizeof(u32), + IA_VERTICES_COUNT, + IA_VERTICES_COUNT + sizeof(u32), + IA_PRIMITIVES_COUNT, + IA_PRIMITIVES_COUNT + sizeof(u32), + VS_INVOCATION_COUNT, + VS_INVOCATION_COUNT + sizeof(u32), + GS_INVOCATION_COUNT, + GS_INVOCATION_COUNT + sizeof(u32), + GS_PRIMITIVES_COUNT, + GS_PRIMITIVES_COUNT + sizeof(u32), CL_INVOCATION_COUNT, CL_INVOCATION_COUNT + sizeof(u32), + CL_PRIMITIVES_COUNT, + CL_PRIMITIVES_COUNT + sizeof(u32), + PS_INVOCATION_COUNT, + PS_INVOCATION_COUNT + sizeof(u32), + PS_DEPTH_COUNT, + PS_DEPTH_COUNT + sizeof(u32), GEN7_SO_NUM_PRIMS_WRITTEN(0), GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32), GEN7_SO_NUM_PRIMS_WRITTEN(1), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 232ad0c..4dd5541 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -356,6 +356,8 @@ #define MI_MATH MI_INSTR(0x1A, 0) #define MI_UPDATE_GTT MI_INSTR(0x23, 0) #define MI_CLFLUSH MI_INSTR(0x27, 0) +#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) +#define MI_REPORT_PERF_COUNT_GGTT (1<<0) #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) @@ -385,7 +387,18 @@ */ #define BCS_SWCTRL 0x22200 +#define HS_INVOCATION_COUNT 0x2300 +#define DS_INVOCATION_COUNT 0x2308 +#define IA_VERTICES_COUNT 0x2310 +#define IA_PRIMITIVES_COUNT 0x2318 +#define VS_INVOCATION_COUNT 0x2320 +#define GS_INVOCATION_COUNT 0x2328 +#define GS_PRIMITIVES_COUNT 0x2330 #define CL_INVOCATION_COUNT 0x2338 +#define CL_PRIMITIVES_COUNT 0x2340 +#define PS_INVOCATION_COUNT 0x2348 +#define PS_DEPTH_COUNT 0x2350 + /* There are the 4 64-bit counter registers, one for each stream output */ #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)