From patchwork Mon Dec 9 12:43:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 3310841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AA50EC0D4A for ; Mon, 9 Dec 2013 12:43:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A1C972023F for ; Mon, 9 Dec 2013 12:43:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F268F201EF for ; Mon, 9 Dec 2013 12:43:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A57F3FAE3A; Mon, 9 Dec 2013 04:43:17 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qa0-f49.google.com (mail-qa0-f49.google.com [209.85.216.49]) by gabe.freedesktop.org (Postfix) with ESMTP id C25B3FAE3A for ; Mon, 9 Dec 2013 04:43:12 -0800 (PST) Received: by mail-qa0-f49.google.com with SMTP id ii20so2538497qab.8 for ; Mon, 09 Dec 2013 04:43:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4AROJfWsOFjdoaEnHxQ9AY6kqnyZu6DwZJZLqLhxQhc=; b=T5T3+c9EjSDHE50FzdmhgbV3nXM9pCBYdMj5ld0Egz08g5ZzP4f+eLiZh0yOvN1Eq9 imrGBLqDXf2gwra0K6wfv8Dd/AperZwAeJJPrRWfdhDZmVuNzuyCSpBsNXgRIaHQtjkA +Y4t+xeBbygC6xzl07mHWnTeTOCyQ2gwBr83sL4VqjEOJSvjDtI39tuQF2rCAWxqBh1V 2AfLxkqO8+qmb6IOqBkiAy3wBMR/44NXMiI6GfIbNxa2Hi0YqrU68Vs8IhhvuJYh8n0f bX4edNwIr3fuhFmV4i8NfjqXgNlVk8TuQ+JUIRFCdE1VmHN7yEVAaBGJoeoPTZyMdNd+ 4V5w== X-Received: by 10.224.80.195 with SMTP id u3mr33872075qak.94.1386592992333; Mon, 09 Dec 2013 04:43:12 -0800 (PST) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id u17sm29462116qeb.4.2013.12.09.04.43.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Dec 2013 04:43:11 -0800 (PST) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Dec 2013 10:43:03 -0200 Message-Id: <1386592983-3529-9-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1386592983-3529-1-git-send-email-rodrigo.vivi@gmail.com> References: <1386592983-3529-1-git-send-email-rodrigo.vivi@gmail.com> Cc: Deepak S Subject: [Intel-gfx] [PATCH 8/8] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v3 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak S On VLV, FIFO will be shared by both SW and HW. So, we read the free entries through register and update dev_priv variable and wait for only 20 entries to be free v2: Apply mask when we read the number of free FIFO entries (Ville). v3: Mask applied after reading the register (Deepak). Signed-off-by: Deepak S Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_uncore.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 0db5472..b7dec19 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -150,6 +150,13 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; + /* On VLV, FIFO will be shared by both SW and HW. + * So, we need to read the FREE_ENTRIES everytime */ + if (IS_VALLEYVIEW(dev_priv->dev)) + dev_priv->uncore.fifo_count = + __raw_i915_read32(dev_priv, GTFIFOCTL) & + GT_FIFO_FREE_ENTRIES_MASK; + if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;