From patchwork Fri Jan 17 03:06:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Previte X-Patchwork-Id: 3501761 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id ED3169F32F for ; Fri, 17 Jan 2014 03:06:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 15B6520170 for ; Fri, 17 Jan 2014 03:06:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 45E3B20165 for ; Fri, 17 Jan 2014 03:06:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 392A7105B9A for ; Thu, 16 Jan 2014 19:06:34 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f174.google.com (mail-pd0-f174.google.com [209.85.192.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D064FD74E for ; Thu, 16 Jan 2014 19:06:23 -0800 (PST) Received: by mail-pd0-f174.google.com with SMTP id w10so3414812pde.19 for ; Thu, 16 Jan 2014 19:06:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=7YwFLVqhgOEDM/v5JIdGqIRtOqDGwaEKpMkl22JWCS4=; b=oRz+mdzmFUZ6BrHA92ewfCQNNjr8hSi/6MzYIumpY+QyO5ZT8nZjTx+9S8vqbgw4Sv JLBkKBgH7qJQeMU/KtqJldG00J8zuvc+0OnkO39Gp6zn0D8wu6BbXvxdImnZawpuUOkO pgHYiJzM06ouklUm/MhGVnCrVczrpqWsKXLIiEj1nQjC35ikGjRoByjeEZJbYUMR8VtJ cZI2s+LHAHOdkf0jhEQxeb1HLfEtHNRzOFBfzoXjX8SZcl1W2a2KPhbcH+rQjxXaSkK6 MWtDnXDX4DqN+U4Kw3JGc+/kXeN5eXN2NEhuLPw4zHNYAZUmej8BNvImVPkb03TPmknU vJIg== X-Received: by 10.68.194.71 with SMTP id hu7mr14017725pbc.68.1389927982236; Thu, 16 Jan 2014 19:06:22 -0800 (PST) Received: from localhost.localdomain (ip70-162-72-129.ph.ph.cox.net. [70.162.72.129]) by mx.google.com with ESMTPSA id zc6sm25020004pab.18.2014.01.16.19.06.20 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 16 Jan 2014 19:06:21 -0800 (PST) From: Todd Previte To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Jan 2014 20:06:08 -0700 Message-Id: <1389927968-2473-1-git-send-email-tprevite@gmail.com> X-Mailer: git-send-email 1.8.1.2 Subject: [Intel-gfx] [PATCH] drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7df5085..f92d1c0 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) case DP_LINK_BW_2_7: break; case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ - max_link_bw = DP_LINK_BW_2_7; + if (intel_dp->dpcd[DP_DPCD_REV] == 0x12) + max_link_bw = DP_LINK_BW_5_4; + else + max_link_bw = DP_LINK_BW_2_7; break; default: WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", @@ -805,9 +808,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_connector *intel_connector = intel_dp->attached_connector; int lane_count, clock; int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); - int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; + /* Conveniently, the link BW constants become indices with a shift...*/ + int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; int bpp, mode_rate; - static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; + static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; int link_avail, link_clock; if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) @@ -2621,10 +2625,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) bool channel_eq = false; int tries, cr_tries; uint32_t DP = intel_dp->DP; + uint32_t training_pattern = DP_TRAINING_PATTERN_2; + + /* Training Pattern 3 for HBR2 */ + if (intel_dp->link_bw == DP_LINK_BW_5_4) + training_pattern = DP_TRAINING_PATTERN_3; /* channel equalization */ if (!intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to start channel equalization\n"); return; @@ -2652,7 +2661,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE); cr_tries++; continue; @@ -2668,7 +2677,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) intel_dp_link_down(intel_dp); intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE); tries = 0; cr_tries++;