From patchwork Fri Jan 17 15:51:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3505921 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2FF939F2E9 for ; Fri, 17 Jan 2014 15:51:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 48BAD200D7 for ; Fri, 17 Jan 2014 15:51:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2E1A920172 for ; Fri, 17 Jan 2014 15:51:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55F92106880; Fri, 17 Jan 2014 07:51:54 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qe0-f54.google.com (mail-qe0-f54.google.com [209.85.128.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 38F22106798 for ; Fri, 17 Jan 2014 07:51:36 -0800 (PST) Received: by mail-qe0-f54.google.com with SMTP id df13so3605669qeb.13 for ; Fri, 17 Jan 2014 07:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x7CvDAum4m8MF2K/0EF8PcAd3ZObmrUQ0CGWv5pH0Jw=; b=Y0QY3cYjwPHTjCGYgjHBLrZm0i4+XVGUq4gvlz4Bk7G2FPPLOONIXGoxvTsFqUpF9p aPqJAa1nGJfaxSdEbczYL3FpHSWqzTU30+KyTehUCYmoyF9XZazvp9KGMUBFg8DIajhM BOzNL2C8qbFl1Ij5gaYX5PdaQQzwNfyKN1wh4OFJ44vbHWrhS4Rya272Pi9rmKc14bYN feEPXNhmKcO4xSzmFqjPwj6BKcrLJmliH8l3rwIKymHRtqJbYydyoMbh7ILD/z+XIYLI +sFg8p5apixz+KSY2pnpanbAlWP24NQ1Cy90XpErWf0AxDu1+pielttWYthlaBbjXUso ntSg== X-Received: by 10.140.41.234 with SMTP id z97mr3964723qgz.89.1389973895615; Fri, 17 Jan 2014 07:51:35 -0800 (PST) Received: from localhost.localdomain ([177.96.29.155]) by mx.google.com with ESMTPSA id w104sm2901857qge.5.2014.01.17.07.51.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Jan 2014 07:51:35 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Jan 2014 13:51:12 -0200 Message-Id: <1389973873-2005-4-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1389973873-2005-1-git-send-email-przanoni@gmail.com> References: <1389973873-2005-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 7/3] drm/i915: remove wait_for_vblank argument form intel_enable_pipe X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni Add a nice comment explaining why we shouldn't wait for a vblank on all cases, wait based on the HW gen, and add a comment saying we should probably skip that wait on some of the previous HW gens. Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_display.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b110da8..9f356f9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1745,12 +1745,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) /** * intel_enable_pipe - enable a pipe, asserting requirements * @crtc: crtc responsible for the pipe - * @wait_for_vblank: whether we should for a vblank or not after enabling it * * Enable @crtc's pipe, making sure that various hardware specific requirements * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. */ -static void intel_enable_pipe(struct intel_crtc *crtc, bool wait_for_vblank) +static void intel_enable_pipe(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -1797,7 +1796,15 @@ static void intel_enable_pipe(struct intel_crtc *crtc, bool wait_for_vblank) I915_WRITE(reg, val | PIPECONF_ENABLE); POSTING_READ(reg); - if (wait_for_vblank) + + /* + * There's no guarantee the pipe will really start running now. It + * depends on the Gen, the output type and the relative order between + * pipe and plane enabling. Avoid waiting on HSW+ since it's not + * necessary. + * TODO: audit the previous gens. + */ + if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) intel_wait_for_vblank(dev_priv->dev, pipe); } @@ -3561,7 +3568,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) intel_crtc_load_lut(crtc); intel_update_watermarks(crtc); - intel_enable_pipe(intel_crtc, true); + intel_enable_pipe(intel_crtc); intel_enable_primary_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -3706,7 +3713,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_ddi_enable_transcoder_func(crtc); intel_update_watermarks(crtc); - intel_enable_pipe(intel_crtc, false); + intel_enable_pipe(intel_crtc); if (intel_crtc->config.has_pch_encoder) lpt_pch_enable(crtc); @@ -4131,7 +4138,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_crtc_load_lut(crtc); intel_update_watermarks(crtc); - intel_enable_pipe(intel_crtc, true); + intel_enable_pipe(intel_crtc); intel_enable_primary_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -4169,7 +4176,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) intel_crtc_load_lut(crtc); intel_update_watermarks(crtc); - intel_enable_pipe(intel_crtc, true); + intel_enable_pipe(intel_crtc); intel_enable_primary_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); /* The fixup needs to happen before cursor is enabled */