From patchwork Fri Jan 17 16:58:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Previte X-Patchwork-Id: 3506321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 34A2E9F169 for ; Fri, 17 Jan 2014 17:01:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 070F820131 for ; Fri, 17 Jan 2014 17:01:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D516A200E9 for ; Fri, 17 Jan 2014 17:01:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 423A1FCED8; Fri, 17 Jan 2014 09:01:33 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f51.google.com (mail-pa0-f51.google.com [209.85.220.51]) by gabe.freedesktop.org (Postfix) with ESMTP id CEDA2FC165 for ; Fri, 17 Jan 2014 08:59:21 -0800 (PST) Received: by mail-pa0-f51.google.com with SMTP id ld10so2045910pab.38 for ; Fri, 17 Jan 2014 08:59:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FI4t17sRb1LzQuVApTwjs5wulCz+GrEKIT7rEv2gS5U=; b=pHwHN2EUxwrfDnMyF/yL8zvHP4LcbTRSw8kxrA8D+tC/oER4hoVVU0TWWj2jVMhfgg azFw2KPjHoY26Ssckc1Fpc+6Jf5x9/QtKvki2sawnBMdF/xhOc7MgpqjgA2weS9uVukC y0URXSV8gQqj3tC02va6rPAj3PhG+5mtYiLkOm8gTZ1ATWDWif3WRnq1EhqndcFwMR+i W/OxaOU/3s45OBpx3EOd4401lRcvvfUmMjR74GrtEQ6Am03VK9x8BgNCy1o3QddZEWk0 +LE/+pPjY4BJFENEURZm6cIaYH+BKtdZr134ebVdsTFgQCR5FvCd43hidxWu+zAL5Qfe Yzzw== X-Received: by 10.66.233.71 with SMTP id tu7mr3355826pac.22.1389977961301; Fri, 17 Jan 2014 08:59:21 -0800 (PST) Received: from localhost.localdomain (ip70-162-72-129.ph.ph.cox.net. [70.162.72.129]) by mx.google.com with ESMTPSA id xu8sm32509036pab.0.2014.01.17.08.59.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 17 Jan 2014 08:59:20 -0800 (PST) From: Todd Previte To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Jan 2014 09:58:03 -0700 Message-Id: <1389977883-4153-2-git-send-email-tprevite@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1389977883-4153-1-git-send-email-tprevite@gmail.com> References: <1389927968-2473-1-git-send-email-tprevite@gmail.com> <1389977883-4153-1-git-send-email-tprevite@gmail.com> Subject: [Intel-gfx] [PATCH] drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2. V2: - Added training pattern 3 flag to intel_dp struct - Added check for appropriate hardware to 5.4Ghz link rate configuration - Added a check for TPS3 supprt in the DPCD read - Adjusted channel equalization to use TPS3 when appropriate - Cleaned up whitespace Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_dp.c | 30 ++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7df5085..fd87c37 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -102,7 +102,11 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) case DP_LINK_BW_2_7: break; case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ - max_link_bw = DP_LINK_BW_2_7; + if ((IS_HSW(dev) || (INTEL_INFO(dev)->gen >= 8)) && + (intel_dp->dpcd[DP_DPCD_REV] >= 0x12)) + max_link_bw = DP_LINK_BW_5_4; + else + max_link_bw = DP_LINK_BW_2_7; break; default: WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", @@ -805,9 +809,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_connector *intel_connector = intel_dp->attached_connector; int lane_count, clock; int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); - int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; + /* Conveniently, the link BW constants become indices with a shift...*/ + int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; int bpp, mode_rate; - static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; + static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; int link_avail, link_clock; if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) @@ -2621,10 +2626,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) bool channel_eq = false; int tries, cr_tries; uint32_t DP = intel_dp->DP; + uint32_t training_pattern = DP_TRAINING_PATTERN_2; + + /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ + if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) + training_pattern = DP_TRAINING_PATTERN_3; /* channel equalization */ if (!intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to start channel equalization\n"); return; @@ -2652,7 +2662,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE); cr_tries++; continue; @@ -2668,7 +2678,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) intel_dp_link_down(intel_dp); intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE); tries = 0; cr_tries++; @@ -2810,6 +2820,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) } } + /* Training Pattern 3 support */ + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && + intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { + intel_dp->use_tps3 = true; + DRM_DEBUG_KMS("Displayport TPS3 supported"); + } else + intel_dp->use_tps3 = false; + if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) return true; /* native DP sink */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9841f78..e934d8d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -488,6 +488,7 @@ struct intel_dp { struct delayed_work panel_vdd_work; bool want_panel_vdd; bool psr_setup_done; + bool use_tps3; struct intel_connector *attached_connector; };