From patchwork Wed Jan 22 03:45:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: akash.goel@intel.com X-Patchwork-Id: 3521681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 47E14C02DC for ; Wed, 22 Jan 2014 03:44:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8E90B20122 for ; Wed, 22 Jan 2014 03:44:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CEB7320108 for ; Wed, 22 Jan 2014 03:44:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F315AFB72F; Tue, 21 Jan 2014 19:44:07 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id CDCA3FB72B for ; Tue, 21 Jan 2014 19:44:01 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 21 Jan 2014 19:44:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,697,1384329600"; d="scan'208";a="468779899" Received: from akashgoe-desktop.iind.intel.com ([10.223.82.34]) by fmsmga002.fm.intel.com with ESMTP; 21 Jan 2014 19:43:33 -0800 From: akash.goel@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 22 Jan 2014 09:15:06 +0530 Message-Id: <1390362310-15963-3-git-send-email-akash.goel@intel.com> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1390362310-15963-1-git-send-email-akash.goel@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> Cc: Akash Goel Subject: [Intel-gfx] [PATCH 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaReadAfterWriteHazard' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel Added a new rendering specific Workaround 'WaReadAfterWriteHazard'. In this WA, need to add 12 MI Store Dword commands to ensure proper flush of h/w pipeline. Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_ringbuffer.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 133d273..e8ec536 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2167,6 +2167,31 @@ intel_ring_flush_all_caches(struct intel_ring_buffer *ring) trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); + if (IS_VALLEYVIEW(ring->dev)) { + /* + * WaReadAfterWriteHazard + * Send a number of Store Data commands here to finish + * flushing hardware pipeline.This is needed in the case + * where the next workload tries reading from the same + * surface that this batch writes to. Without these StoreDWs, + * not all of the data will actually be flushd to the surface + * by the time the next batch starts reading it, possibly + * causing a small amount of corruption. + */ + int i; + ret = intel_ring_begin(ring, 4 * 12); + if (ret) + return ret; + for (i = 0; i < 12; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << + MI_STORE_DWORD_INDEX_SHIFT); + intel_ring_emit(ring, 0); + intel_ring_emit(ring, MI_NOOP); + } + intel_ring_advance(ring); + } + ring->gpu_caches_dirty = false; return 0; }