From patchwork Wed Jan 22 03:45:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: akash.goel@intel.com X-Patchwork-Id: 3521711 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 425CEC02DC for ; Wed, 22 Jan 2014 03:44:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 61C9D20108 for ; Wed, 22 Jan 2014 03:44:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6F35B20125 for ; Wed, 22 Jan 2014 03:44:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2CD3CFB6E3; Tue, 21 Jan 2014 19:44:28 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id AD792FB732 for ; Tue, 21 Jan 2014 19:44:07 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 21 Jan 2014 19:44:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,697,1384329600"; d="scan'208";a="468779927" Received: from akashgoe-desktop.iind.intel.com ([10.223.82.34]) by fmsmga002.fm.intel.com with ESMTP; 21 Jan 2014 19:43:46 -0800 From: akash.goel@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 22 Jan 2014 09:15:10 +0530 Message-Id: <1390362310-15963-7-git-send-email-akash.goel@intel.com> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1390362310-15963-1-git-send-email-akash.goel@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> Cc: Akash Goel Subject: [Intel-gfx] [PATCH 6/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel This workaround is needed on VLV for the HW context feature. It is used after adding the mi_set_context command in ring buffer for Hw context switch. As per the spec "The software must send a pipe_control with a CS stall and a post sync operation and then a dummy DRAW after every MI_SET_CONTEXT and after any PIPELINE_SELECT that is enabling 3D mode". Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/i915_gem_context.c | 64 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 4 files changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index ebe0f67..62a5362 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -532,6 +532,58 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); } +static inline void +mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring) +{ + u32 scratch_addr; + u32 flags = 0; + + /* + * Check if we have the scratch page allocated needed + * for the Pipe Control command, otherwise don't apply + * the dummmy 3d primitive workaround & add NOOPs instead + */ + if (get_pipe_control_scratch_addr(ring)) { + /* Actual scratch location is at 128 bytes offset */ + scratch_addr = get_pipe_control_scratch_addr(ring) + 128; + + /* + * WaSendDummy3dPrimitveAfterSetContext + * Software must send a pipe_control with a CS stall + * and a post sync operation and then a dummy DRAW after + * every MI_SET_CONTEXT and after any PIPELINE_SELECT that + * is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command + * with Indirect Parameter Enable set to 0, UAV Coherency + * Required set to 0, Predicate Enable set to 0, + * End Offset Enable set to 0, and Vertex Count Per Instance + * set to 0, All other parameters are a don't care. + */ + + /* + * Add a pipe control with CS Stall and postsync op + * before dummy 3D_PRIMITIVE + */ + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(ring, flags); + intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); + intel_ring_emit(ring, 0); + + /* Add a dummy 3D_PRIMITVE */ + intel_ring_emit(ring, GFX_OP_3DPRIMITIVE()); + intel_ring_emit(ring, 4); /* PrimTopoType*/ + intel_ring_emit(ring, 0); /* VertexCountPerInstance */ + intel_ring_emit(ring, 0); /* StartVertexLocation */ + intel_ring_emit(ring, 0); /* InstanceCount */ + intel_ring_emit(ring, 0); /* StartInstanceLocation */ + intel_ring_emit(ring, 0); /* BaseVertexLocation */ + } else { + int i; + for (i = 0; i < 11; i++) + intel_ring_emit(ring, MI_NOOP); + } +} + static inline int mi_set_context(struct intel_ring_buffer *ring, struct i915_hw_context *new_context, @@ -550,7 +602,10 @@ mi_set_context(struct intel_ring_buffer *ring, return ret; } - ret = intel_ring_begin(ring, 6); + if (IS_VALLEYVIEW(ring->dev)) + ret = intel_ring_begin(ring, 6+4+8); + else + ret = intel_ring_begin(ring, 6); if (ret) return ret; @@ -571,7 +626,12 @@ mi_set_context(struct intel_ring_buffer *ring, intel_ring_emit(ring, MI_NOOP); if (IS_GEN7(ring->dev)) - intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); + if (IS_VALLEYVIEW(ring->dev)) { + mi_set_context_dummy3d_prim_wa(ring); + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); + intel_ring_emit(ring, MI_NOOP); + } else + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); else intel_ring_emit(ring, MI_NOOP); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d829754..649106d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -335,6 +335,9 @@ #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define GFX_OP_3DPRIMITIVE() \ + ((0x3<<29)|(0x3<<27)|(0x3<<24)| \ + (0x0<<16)|(0x0<<10)|(0x0<<8)|(7-2)) /* * Reset registers diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8b99df2..a93b631 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -556,6 +556,15 @@ err: return ret; } +u32 +get_pipe_control_scratch_addr(struct intel_ring_buffer *ring) +{ + if (ring->scratch.obj == NULL) + return 0; + + return ring->scratch.gtt_offset; +} + static int init_render_ring(struct intel_ring_buffer *ring) { struct drm_device *dev = ring->dev; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 71a73f4..2ae6029 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -257,6 +257,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev); u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); void intel_ring_setup_status_page(struct intel_ring_buffer *ring); +u32 get_pipe_control_scratch_addr(struct intel_ring_buffer *ring); static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) {