From patchwork Wed Jan 22 19:52:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3525281 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E054B9F1C3 for ; Wed, 22 Jan 2014 19:54:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F21020179 for ; Wed, 22 Jan 2014 19:54:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1C6012011D for ; Wed, 22 Jan 2014 19:54:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CE1EFB8C7; Wed, 22 Jan 2014 11:54:29 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gg0-f179.google.com (mail-gg0-f179.google.com [209.85.161.179]) by gabe.freedesktop.org (Postfix) with ESMTP id 114C7FBBC5 for ; Wed, 22 Jan 2014 11:53:35 -0800 (PST) Received: by mail-gg0-f179.google.com with SMTP id e5so3200404ggh.24 for ; Wed, 22 Jan 2014 11:53:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9g7RO+uNsA43RWrtbj49Vv3eLMPNrx+kNkj0y0g5tvU=; b=NQlM2aY5YSnlO0m2YQkEEs4e26W7Aa+zXNl5NljetFh08K1PidkrwLx3YmwSZCxGN3 W/x3LKeDaK+LFDgnGDHvy14T9U9XvX/Ik2Gwea4cgkRJqH2UXbGbg+VTT8tX19RaKW0q y2xGSLT5TSl8XVtZKd+1lAP+H7UWCZXUKHAnGDKXRxTd9Ex5Tq8XhZyjg/M3c9cWzVeo 7bvMh3/rpLYz05hI0x28e5XFWN2fbRehyaJD+OXRoCbKm44LSXNRUIlzFV1LtFGhQMMM eXMi/ymDGEKjjPUBarTJ06cgmcjrKIbmWejWvrqjHyHmf9Rsa8QgI+4vcB7+Qxoj/Y7V aWCA== X-Received: by 10.236.155.199 with SMTP id j47mr2112958yhk.116.1390420415471; Wed, 22 Jan 2014 11:53:35 -0800 (PST) Received: from localhost.localdomain ([187.112.59.220]) by mx.google.com with ESMTPSA id f78sm27457275yhp.12.2014.01.22.11.53.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Jan 2014 11:53:34 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Wed, 22 Jan 2014 17:52:32 -0200 Message-Id: <1390420357-23669-15-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1390420357-23669-1-git-send-email-przanoni@gmail.com> References: <1390420357-23669-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 14/19] drm/i915: enable SDEIER later X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni On the preinstall stage we should just disable all the interrupts, but we currently enable all the south display interrupts due to the way we touch SDEIER at the IRQ handlers (note: they are still masked and our IRQ handler is disabled). Instead of doing that, let's make the preinstall stage just disable all the south interrupts, and do the proper interrupt dance/ordering at the postinstall stage, including an assert to check if everything is behaving as expected. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 60f4c46..ce6a8f3 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2646,13 +2646,24 @@ static void ibx_irq_preinstall(struct drm_device *dev) if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) I915_WRITE(SERR_INT, 0xffffffff); +} - /* - * SDEIER is also touched by the interrupt handler to work around missed - * PCH interrupts. Hence we can't update it after the interrupt handler - * is enabled - instead we unconditionally enable all PCH interrupt - * sources here, but then only unmask them as needed with SDEIMR. - */ +/* + * SDEIER is also touched by the interrupt handler to work around missed PCH + * interrupts. Hence we can't update it after the interrupt handler is enabled - + * instead we unconditionally enable all PCH interrupt sources here, but then + * only unmask them as needed with SDEIMR. + * + * This function needs to be called before interrupts are enabled. + */ +static void ibx_irq_pre_postinstall(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (HAS_PCH_NOP(dev)) + return; + + WARN_ON(I915_READ(SDEIER) != 0); I915_WRITE(SDEIER, 0xffffffff); POSTING_READ(SDEIER); } @@ -2858,6 +2869,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) dev_priv->irq_mask = ~display_mask; + ibx_irq_pre_postinstall(dev); + GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); gen5_gt_irq_postinstall(dev); @@ -2980,6 +2993,8 @@ static int gen8_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + ibx_irq_pre_postinstall(dev); + gen8_gt_irq_postinstall(dev_priv); gen8_de_irq_postinstall(dev_priv);