From patchwork Tue Feb 18 03:01:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3666951 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 07C3FBF13A for ; Tue, 18 Feb 2014 03:02:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 10FA72012E for ; Tue, 18 Feb 2014 03:02:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0CB7D20107 for ; Tue, 18 Feb 2014 03:02:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 60010FA954; Mon, 17 Feb 2014 19:02:29 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id EF748FA92A for ; Mon, 17 Feb 2014 19:02:01 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 17 Feb 2014 19:02:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,499,1389772800"; d="scan'208";a="484967294" Received: from unknown (HELO ironside.amr.corp.intel.com) ([10.255.13.201]) by orsmga002.jf.intel.com with ESMTP; 17 Feb 2014 19:02:00 -0800 From: Ben Widawsky To: Intel GFX Date: Mon, 17 Feb 2014 19:01:46 -0800 Message-Id: <1392692512-2268-6-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.5.5 In-Reply-To: <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> References: <1390969547-1018-2-git-send-email-benjamin.widawsky@intel.com> <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 05/11] drm/i915: remove rps local variables X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With the renamed RPS struct members, it's easier to skip the local variables which no longer clarify anything, and if anything just make the code harder to read. The real motivation for this patch is actually the next patch, which attempts to consolidate some of the functionality. Cc: Jeff McGee Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_sysfs.c | 37 ++++++++++++------------------------- drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++-------------- 2 files changed, 27 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 27cf344..6f83cca 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -313,7 +313,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, struct drm_minor *minor = dev_to_drm_minor(kdev); struct drm_device *dev = minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 val, hw_max, hw_min, non_oc_max; + u32 val; ssize_t ret; ret = kstrtou32(buf, 0, &val); @@ -324,27 +324,19 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, mutex_lock(&dev_priv->rps.hw_lock); - if (IS_VALLEYVIEW(dev_priv->dev)) { + if (IS_VALLEYVIEW(dev_priv->dev)) val = vlv_freq_opcode(dev_priv, val); - - hw_max = dev_priv->rps.max_freq_hardlimit; - hw_min = dev_priv->rps.min_freq_hardlimit; - non_oc_max = hw_max; - } else { + else val /= GT_FREQUENCY_MULTIPLIER; - hw_max = dev_priv->rps.max_freq_overclock; - non_oc_max = dev_priv->rps.max_freq_hardlimit; - hw_min = dev_priv->rps.min_freq_hardlimit; - } - - if (val < hw_min || val > hw_max || + if (val < dev_priv->rps.min_freq_hardlimit || + val > dev_priv->rps.max_freq_overclock || val < dev_priv->rps.min_freq_softlimit) { mutex_unlock(&dev_priv->rps.hw_lock); return -EINVAL; } - if (val > non_oc_max) + if (val > dev_priv->rps.max_freq_hardlimit) DRM_DEBUG("User requested overclocking to %d\n", val * GT_FREQUENCY_MULTIPLIER); @@ -393,7 +385,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, struct drm_minor *minor = dev_to_drm_minor(kdev); struct drm_device *dev = minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 val, hw_max, hw_min; + u32 val; ssize_t ret; ret = kstrtou32(buf, 0, &val); @@ -404,19 +396,14 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, mutex_lock(&dev_priv->rps.hw_lock); - if (IS_VALLEYVIEW(dev)) { + if (IS_VALLEYVIEW(dev)) val = vlv_freq_opcode(dev_priv, val); - - hw_max = dev_priv->rps.max_freq_hardlimit; - hw_min = dev_priv->rps.min_freq_hardlimit; - } else { + else val /= GT_FREQUENCY_MULTIPLIER; - hw_max = dev_priv->rps.max_freq_overclock; - hw_min = dev_priv->rps.min_freq_hardlimit; - } - - if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { + if (val < dev_priv->rps.min_freq_hardlimit || + val > dev_priv->rps.max_freq_overclock || + val > dev_priv->rps.max_freq_softlimit) { mutex_unlock(&dev_priv->rps.hw_lock); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 341c154..e63515a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3321,7 +3321,7 @@ static void gen6_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_ring_buffer *ring; - u32 rp_state_cap, hw_max, hw_min; + u32 rp_state_cap; u32 gt_perf_status; u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; u32 gtfifodbg; @@ -3350,19 +3350,19 @@ static void gen6_enable_rps(struct drm_device *dev) gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); /* In units of 50MHz */ - dev_priv->rps.max_freq_overclock = hw_max = rp_state_cap & 0xff; - hw_min = (rp_state_cap >> 16) & 0xff; + dev_priv->rps.nominal_freq = (rp_state_cap >> 16) & 0xff; dev_priv->rps.min_freq_hardlimit = (rp_state_cap >> 8) & 0xff; dev_priv->rps.max_freq_hardlimit = (rp_state_cap >> 0) & 0xff; + dev_priv->rps.max_freq_overclock = dev_priv->rps.max_freq_hardlimit; dev_priv->rps.nominal_freq = dev_priv->rps.min_freq_hardlimit; dev_priv->rps.cur_freq = 0; /* Preserve min/max settings in case of re-init */ if (dev_priv->rps.max_freq_softlimit == 0) - dev_priv->rps.max_freq_softlimit = hw_max; + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq_hardlimit; if (dev_priv->rps.min_freq_softlimit == 0) - dev_priv->rps.min_freq_softlimit = hw_min; + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq_hardlimit; /* disable the counters and set deterministic thresholds */ I915_WRITE(GEN6_RC_CONTROL, 0); @@ -3590,7 +3590,7 @@ static void valleyview_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_ring_buffer *ring; - u32 gtfifodbg, val, hw_max, hw_min, rc6_mode = 0; + u32 gtfifodbg, val, rc6_mode = 0; int i; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -3652,27 +3652,28 @@ static void valleyview_enable_rps(struct drm_device *dev) vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), dev_priv->rps.cur_freq); - dev_priv->rps.max_freq_overclock = hw_max = valleyview_rps_max_freq(dev_priv); + dev_priv->rps.max_freq_hardlimit = valleyview_rps_max_freq(dev_priv); + dev_priv->rps.max_freq_overclock = dev_priv->rps.max_freq_hardlimit; DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", - vlv_gpu_freq(dev_priv, hw_max), - hw_max); + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_hardlimit), + dev_priv->rps.max_freq_hardlimit); dev_priv->rps.nominal_freq = valleyview_rps_rpe_freq(dev_priv); DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", vlv_gpu_freq(dev_priv, dev_priv->rps.nominal_freq), dev_priv->rps.nominal_freq); - hw_min = valleyview_rps_min_freq(dev_priv); + dev_priv->rps.min_freq_hardlimit = valleyview_rps_min_freq(dev_priv); DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", - vlv_gpu_freq(dev_priv, hw_min), - hw_min); + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_hardlimit), + dev_priv->rps.min_freq_hardlimit); /* Preserve min/max settings in case of re-init */ if (dev_priv->rps.max_freq_softlimit == 0) - dev_priv->rps.max_freq_softlimit = hw_max; + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq_hardlimit; if (dev_priv->rps.min_freq_softlimit == 0) - dev_priv->rps.min_freq_softlimit = hw_min; + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq_hardlimit; DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", vlv_gpu_freq(dev_priv, dev_priv->rps.nominal_freq),