From patchwork Thu Feb 20 06:27:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3684641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B05459F35F for ; Thu, 20 Feb 2014 06:27:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC974201F0 for ; Thu, 20 Feb 2014 06:27:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6D6A6201B6 for ; Thu, 20 Feb 2014 06:27:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 485D8FAFD7; Wed, 19 Feb 2014 22:27:25 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id E589DFAFD7 for ; Wed, 19 Feb 2014 22:27:23 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 19 Feb 2014 22:27:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,510,1389772800"; d="scan'208";a="484622242" Received: from unknown (HELO ironside.amr.corp.intel.com) ([10.255.14.6]) by fmsmga002.fm.intel.com with ESMTP; 19 Feb 2014 22:27:22 -0800 From: Ben Widawsky To: Intel GFX Date: Wed, 19 Feb 2014 22:27:20 -0800 Message-Id: <1392877640-20588-1-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1392695814-14489-1-git-send-email-benjamin.widawsky@intel.com> References: <1392695814-14489-1-git-send-email-benjamin.widawsky@intel.com> Cc: "David E. Box" , Ben Widawsky , Kristen Carlson Accardi , Ben Widawsky Subject: [Intel-gfx] [PATCH 11/11] [v4] drm/i915/bdw: Ensure a context is loaded before RC6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP RC6 works a lot like HW contexts in that when the GPU enters RC6 it saves away the state to a context, and loads it upon wake. It's to be somewhat expected that BIOS will not set up valid GPU state. As a result, if loading bad state can cause the GPU to get angry, it would make sense then that we need to load state first. There are two ways in which we can do this: 1. Create 3d state in the driver, load it up, then enable RC6. 1b. Reuse a known good state, [and if needed,] just bind objects where needed. Then enable RC6. 2. Hold off enabling RC6 until userspace has had a chance to complete batches. There has been discussions in the past with #1 as it has been recommended for fixes elsewhere. I'm not opposed to it, I'd just like to do the easy thing now to enable the platform. This patch is a hack that implement option #2. It will defer enabling rc6 until the first batch from userspace has been retired. It suffers two flaws. The first is, if the driver is loaded, but a batch is not submitted/completed, we'll never enter rc6. The other is, it expects userspace to submit a batch with 3d state first. Both of these things are not actual flaws for most users because most users will boot to a graphical composited desktop. Both mesa, and X will always emit the necessary 3d state. Once a context is loaded and we enable rc6, the default context should inherit the proper state because we always inhibit the restore for the default context. This assumes certain things about the workaround/issue itself to which I am not privy (primarily that the indirect state objects don't actually need to exist). With that, there are currently 4 options for BDW: 1. Don't use RC6. 2. Use RC6 and expect a hang on the first batch submitted for every context. 3. Use RC6 and use this patch. 4. Wait for another workaround implementation. NOTE: This patch could be used against other platforms as well. v2: Re-add accidentally dropped hunk (Ben) v3: Now more compilable (Ben) v4: Use the existing enable flag for rc6. This will also make the suspend/resume case work properly, which is broken in v3. Disable rc6 on reset, and defer re-enabling until the first batch. The fact that RC6 residency continues to increment, and that this patch prevents a hang on BDW silicon has been: Tested-by: Kenneth Graunke (v1) Cc: David E. Box Cc: Kristen Carlson Accardi Signed-off-by: Ben Widawsky squash! drm/i915/bdw: Ensure a context is loaded before RC6 --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++ drivers/gpu/drm/i915/intel_display.c | 5 +++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2d05d7c..7fdfc0e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -679,6 +679,8 @@ int i915_reset(struct drm_device *dev) mutex_lock(&dev->struct_mutex); i915_gem_reset(dev); + if (IS_BROADWELL(dev)) + intel_disable_gt_powersave(dev); simulated = dev_priv->gpu_error.stop_rings != 0; @@ -733,7 +735,7 @@ int i915_reset(struct drm_device *dev) * reset and the re-install of drm irq. Skip for ironlake per * previous concerns that it doesn't respond well to some forms * of re-init after reset. */ - if (INTEL_INFO(dev)->gen > 5) { + if (INTEL_INFO(dev)->gen > 5 && !IS_BROADWELL(dev)) { mutex_lock(&dev->struct_mutex); intel_enable_gt_powersave(dev); mutex_unlock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3618bb0..25a97a6 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2420,6 +2420,7 @@ void i915_gem_reset(struct drm_device *dev) void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) { + struct drm_i915_private *dev_priv = ring->dev->dev_private; uint32_t seqno; if (list_empty(&ring->request_list)) @@ -2443,6 +2444,15 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) if (!i915_seqno_passed(seqno, obj->last_read_seqno)) break; + /* Wa: can't find the w/a name. + * This doesn't actually implement the w/a, but it a workaround + * for the workaround. It defers using rc6 until we know valid + * state exists. + */ + if (IS_BROADWELL(ring->dev) && intel_enable_rc6(ring->dev) && + !dev_priv->rps.enabled && ring->id == RCS) + intel_enable_gt_powersave(ring->dev); + i915_gem_object_move_to_inactive(obj); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f19e6ea..72c8e1d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10983,6 +10983,11 @@ void intel_modeset_init_hw(struct drm_device *dev) intel_reset_dpio(dev); + if (IS_BROADWELL(dev)) { + DRM_DEBUG_DRIVER("Deferring RC6 enabling until first batch is complete\n"); + return; + } + mutex_lock(&dev->struct_mutex); intel_enable_gt_powersave(dev); mutex_unlock(&dev->struct_mutex);