From patchwork Thu Feb 27 07:59:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 3731001 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4A1A3BF13A for ; Thu, 27 Feb 2014 08:01:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C316B20218 for ; Thu, 27 Feb 2014 08:01:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9BAE2201CD for ; Thu, 27 Feb 2014 08:01:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24D8A105834; Thu, 27 Feb 2014 00:01:07 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from homiemail-a14.g.dreamhost.com (caiajhbdcagg.dreamhost.com [208.97.132.66]) by gabe.freedesktop.org (Postfix) with ESMTP id CA4C7105834 for ; Thu, 27 Feb 2014 00:01:03 -0800 (PST) Received: from homiemail-a14.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a14.g.dreamhost.com (Postfix) with ESMTP id 8ED26392076; Thu, 27 Feb 2014 00:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=whitecape.org; h=from:to :cc:subject:date:message-id:in-reply-to:references; s= whitecape.org; bh=iTTst4brI5YUm5JuPgvMk/4NoNc=; b=htj848odFNd3AC jUdTqht92xgFL4xHv723owNNNaH6sN+lKSd9T6AZAMJcjAnnKCW3pB7iQMPYWj4y uwLbkueI0Kz5Ly7lxep3nC+Z5rJQb+vGWaMfBuw28S0TA/hKYKUTbc5pAV/4xZN0 LAdueRP/2WfkEgCTyc0R02ATwOHV8= Received: from zidane.shinigami (unknown [50.126.105.238]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: kenneth@whitecape.org) by homiemail-a14.g.dreamhost.com (Postfix) with ESMTPSA id 46520392078; Thu, 27 Feb 2014 00:01:03 -0800 (PST) From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Wed, 26 Feb 2014 23:59:31 -0800 Message-Id: <1393487971-739-2-git-send-email-kenneth@whitecape.org> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1393487971-739-1-git-send-email-kenneth@whitecape.org> References: <1393487971-739-1-git-send-email-kenneth@whitecape.org> Cc: ben@bwidawsk.net Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Add thread stall DOP clock gating workaround on Broadwell. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Ben and I believe this will be necessary on production hardware. Signed-off-by: Kenneth Graunke Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f36d5e0..ade1d71 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5052,6 +5052,7 @@ #define GEN8_ROW_CHICKEN 0xe4f0 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) +#define STALL_DOP_GATING_DISABLE (1<<5) #define GEN7_ROW_CHICKEN2 0xe4f4 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index df8ad21..226591d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4842,6 +4842,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_ROW_CHICKEN, _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); + /* WaDisableThreadStallDopClockGating:bdw */ + I915_WRITE(GEN8_ROW_CHICKEN, + _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); + /* * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for * pre-production hardware