From patchwork Fri Mar 7 23:10:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3795451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9CE3BBF54D for ; Fri, 7 Mar 2014 23:11:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B02EE202E9 for ; Fri, 7 Mar 2014 23:11:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 928FC20304 for ; Fri, 7 Mar 2014 23:11:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36DE5FB66D; Fri, 7 Mar 2014 15:11:51 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yk0-f176.google.com (mail-yk0-f176.google.com [209.85.160.176]) by gabe.freedesktop.org (Postfix) with ESMTP id D79C7FB667 for ; Fri, 7 Mar 2014 15:11:28 -0800 (PST) Received: by mail-yk0-f176.google.com with SMTP id 19so12544430ykq.7 for ; Fri, 07 Mar 2014 15:11:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I365fH+rn8ci7dgwfafLnLH0OBNqgiovpzdT16Pt+s0=; b=0t29GMIpEDdvpeXf0Z0xsn+2TlKrsFNsavFx9FaLcV7nx3OBCqTfIuBJ2118Of/ZD1 ECL83CGbY5BZ09R6fsxSPA1xvM3H4c4Wzw+hQ7960qIj4uvHBTY6VK237gz/pL9OkEy8 x6i72FYqGZ743RcZRpQLBRUx9a1NTTjI9oEwwBVOx1bmpJrqNouioOqggckTO6aNoicl r9XSt2cfNxKavl3rc+dHhyg/Y8fPXBz+MQIHnfZ9HTDymIQHkHOL6fhulrQ5fzws6Xec UMurOgEO4N+GZTvV1BsXqyKQUHxukKu6IOrsdWZvTaVgg7cKFGB15uQp051Q+czVnBkV +DuQ== X-Received: by 10.236.61.115 with SMTP id v79mr5451693yhc.113.1394233888476; Fri, 07 Mar 2014 15:11:28 -0800 (PST) Received: from localhost.localdomain ([177.132.70.215]) by mx.google.com with ESMTPSA id h23sm32556000yhc.0.2014.03.07.15.11.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Mar 2014 15:11:28 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Mar 2014 20:10:36 -0300 Message-Id: <1394233836-3827-21-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1394233836-3827-1-git-send-email-przanoni@gmail.com> References: <1394233836-3827-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 20/20] drm/i915: add POSTING_READs to the IRQ init/reset macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni I previously chose to keep the POSTING_READ calls as something to be done by the macro callers, but the conclusion after discussing this on the mailing list is that leaving the POSTING_READ calls to the macros makes the code safer, and the additional useless register reads shouldn't be noticeable. So move the POSTING_READ calls to the callers. Signed-off-by: Paulo Zanoni Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 79a8196..dee3a3b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -80,11 +80,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; -/* - * IIR can theoretically queue up two events. Be paranoid. - * Also, make sure callers of these macros have something equivalent to a - * POSTING_READ on the IIR register. - * */ +/* IIR can theoretically queue up two events. Be paranoid. */ #define GEN8_IRQ_RESET_NDX(type, which) do { \ I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ POSTING_READ(GEN8_##type##_IMR(which)); \ @@ -92,6 +88,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ POSTING_READ(GEN8_##type##_IIR(which)); \ I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ + POSTING_READ(GEN8_##type##_IIR(which)); \ } while (0) #define GEN5_IRQ_RESET(type) do { \ @@ -101,6 +98,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ I915_WRITE(type##IIR, 0xffffffff); \ POSTING_READ(type##IIR); \ I915_WRITE(type##IIR, 0xffffffff); \ + POSTING_READ(type##IIR); \ } while (0) /* @@ -117,12 +115,14 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ + POSTING_READ(GEN8_##type##_IER(which)); \ } while (0) #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ I915_WRITE(type##IMR, (imr_val)); \ I915_WRITE(type##IER, (ier_val)); \ + POSTING_READ(type##IER); \ } while (0) /* For display hotplug interrupt */ @@ -2843,7 +2843,6 @@ static void gen5_gt_irq_reset(struct drm_device *dev) GEN5_IRQ_RESET(GT); if (INTEL_INFO(dev)->gen >= 6) GEN5_IRQ_RESET(GEN6_PM); - POSTING_READ(GTIIR); } /* drm_dma.h hooks @@ -2917,7 +2916,6 @@ static void gen8_irq_reset(struct drm_device *dev) GEN5_IRQ_RESET(GEN8_DE_PORT_); GEN5_IRQ_RESET(GEN8_DE_MISC_); GEN5_IRQ_RESET(GEN8_PCU_); - POSTING_READ(GEN8_PCU_IIR); ibx_irq_reset(dev); } @@ -3016,7 +3014,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) dev_priv->pm_irq_mask = 0xffffffff; GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); } - POSTING_READ(GTIER); } static int ironlake_irq_postinstall(struct drm_device *dev) @@ -3213,7 +3210,6 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); - POSTING_READ(GEN8_GT_IER(0)); } static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3232,10 +3228,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) for_each_pipe(pipe) GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], de_pipe_enables); - POSTING_READ(GEN8_DE_PIPE_ISR(0)); GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); - POSTING_READ(GEN8_DE_PORT_IER); } static int gen8_irq_postinstall(struct drm_device *dev)