From patchwork Fri Mar 7 23:10:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3795301 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E49B09F1CD for ; Fri, 7 Mar 2014 23:11:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B1C3202EA for ; Fri, 7 Mar 2014 23:11:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2D3C1202F2 for ; Fri, 7 Mar 2014 23:11:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ABB26FADA6; Fri, 7 Mar 2014 15:11:06 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f50.google.com (mail-yh0-f50.google.com [209.85.213.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AB0BFAC1F for ; Fri, 7 Mar 2014 15:11:05 -0800 (PST) Received: by mail-yh0-f50.google.com with SMTP id t59so5016452yho.37 for ; Fri, 07 Mar 2014 15:11:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LMj+R6U7d/HfkHz70ZcX3G5viyckqG7PkaF2Usx+BQk=; b=Ksr+Knd7MUKcAHKtjI9j0bDaO95Cvl1UcZ90tIOXRD7wpLtIlSA75rce/IPEN0kCqI dIeESUNWHCz0dNDnOjhe4s0Us34j8moshAKgz9xRddO1vOauoWtFreZQ8PalKIcsApzx x9qICVMLVKopE5N7at2GWQ5Gn5vS8RFfUunnceXhsKwY8o9P+4jPecxt9hl00+ioUQlA 5wbMDJ4AssnFTfujrCkMBQ3TrOuXg6sMa/yJm6PO3ntwqMAyByJvbPKxkyH5nRZdwCY6 +sIOq+FQrHJsZC8wT/5QK8IgpF5bLigBalt9uO83H3CtYvqF412AXXTuoVGeM9YaoAPg wFrw== X-Received: by 10.236.150.164 with SMTP id z24mr26044098yhj.75.1394233864928; Fri, 07 Mar 2014 15:11:04 -0800 (PST) Received: from localhost.localdomain ([177.132.70.215]) by mx.google.com with ESMTPSA id h23sm32556000yhc.0.2014.03.07.15.11.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Mar 2014 15:11:04 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Mar 2014 20:10:19 -0300 Message-Id: <1394233836-3827-4-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1394233836-3827-1-git-send-email-przanoni@gmail.com> References: <1394233836-3827-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 03/20] drm/i915: use GEN8_IRQ_INIT on GEN5 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni And rename is to GEN5_IRQ_INIT. We have discussed doing equivalent changes on July 2013, and I even sent a patch series for this: "[PATCH 00/15] Unify interrupt register init/reset". Now that the BDW code was merged, I have one more argument in favor of these changes. Here's what really changes with the Gen 5 IRQ init code: - We now clear the IIR registers at preinstall (they are also cleared at postinstall, but we will change that later). - We have an additional POSTING_READ at the IMR register. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 852844d..7be7da1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -80,12 +80,30 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; +/* + * IIR can theoretically queue up two events. Be paranoid. + * Also, make sure callers of these macros have something equivalent to a + * POSTING_READ on the IIR register. + * */ +#define GEN8_IRQ_INIT_NDX(type, which) do { \ + I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ + POSTING_READ(GEN8_##type##_IMR(which)); \ + I915_WRITE(GEN8_##type##_IER(which), 0); \ + I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ + POSTING_READ(GEN8_##type##_IIR(which)); \ + I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ +} while (0) + #define GEN5_IRQ_INIT(type) do { \ I915_WRITE(type##IMR, 0xffffffff); \ + POSTING_READ(type##IMR); \ I915_WRITE(type##IER, 0); \ - POSTING_READ(type##IER); \ + I915_WRITE(type##IIR, 0xffffffff); \ + POSTING_READ(type##IIR); \ + I915_WRITE(type##IIR, 0xffffffff); \ } while (0) + /* For display hotplug interrupt */ static void ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) @@ -2789,6 +2807,7 @@ static void gen5_gt_irq_preinstall(struct drm_device *dev) GEN5_IRQ_INIT(GT); if (INTEL_INFO(dev)->gen >= 6) GEN5_IRQ_INIT(GEN6_PM); + POSTING_READ(GTIIR); } /* drm_dma.h hooks @@ -2843,25 +2862,6 @@ static void gen8_irq_preinstall(struct drm_device *dev) I915_WRITE(GEN8_MASTER_IRQ, 0); POSTING_READ(GEN8_MASTER_IRQ); - /* IIR can theoretically queue up two events. Be paranoid */ -#define GEN8_IRQ_INIT_NDX(type, which) do { \ - I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ - POSTING_READ(GEN8_##type##_IMR(which)); \ - I915_WRITE(GEN8_##type##_IER(which), 0); \ - I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ - POSTING_READ(GEN8_##type##_IIR(which)); \ - I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ - } while (0) - -#define GEN8_IRQ_INIT(type) do { \ - I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ - POSTING_READ(GEN8_##type##_IMR); \ - I915_WRITE(GEN8_##type##_IER, 0); \ - I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ - POSTING_READ(GEN8_##type##_IIR); \ - I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ - } while (0) - GEN8_IRQ_INIT_NDX(GT, 0); GEN8_IRQ_INIT_NDX(GT, 1); GEN8_IRQ_INIT_NDX(GT, 2); @@ -2871,12 +2871,9 @@ static void gen8_irq_preinstall(struct drm_device *dev) GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); } - GEN8_IRQ_INIT(DE_PORT); - GEN8_IRQ_INIT(DE_MISC); - GEN8_IRQ_INIT(PCU); -#undef GEN8_IRQ_INIT -#undef GEN8_IRQ_INIT_NDX - + GEN5_IRQ_INIT(GEN8_DE_PORT_); + GEN5_IRQ_INIT(GEN8_DE_MISC_); + GEN5_IRQ_INIT(GEN8_PCU_); POSTING_READ(GEN8_PCU_IIR); ibx_irq_preinstall(dev);