From patchwork Fri Mar 7 23:10:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3795431 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6E1EBBF540 for ; Fri, 7 Mar 2014 23:11:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B9C2C202E9 for ; Fri, 7 Mar 2014 23:11:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C2F07202F2 for ; Fri, 7 Mar 2014 23:11:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 824ECFB66A; Fri, 7 Mar 2014 15:11:50 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f52.google.com (mail-yh0-f52.google.com [209.85.213.52]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D7D7FB656 for ; Fri, 7 Mar 2014 15:11:09 -0800 (PST) Received: by mail-yh0-f52.google.com with SMTP id a41so4971960yho.25 for ; Fri, 07 Mar 2014 15:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fm4M50EuYykntL390UXlsWzHYjraJtUvkUTr0k+Xcvw=; b=RP6afkRb+anb+IwUavYNgcKxF5fsvQ4yLxa3pIIK5ZFYIidUOShYyfihNv9SsiveMk /hz20SivYbZNeaRXPW8jNsltTdzU4IL7tJkW5Xb2baaWr8DcbtyPhfTCVraze4Pg6Ev8 FPasHdE0f6uvLS/x+eNlFH0aHnKmbd+QwBCjfT2LQSKwGq4YoAvayJ5HxzaqsZ+ircFG AFxvdIpyLARpXKicHoHTRkMf3DgSACIec8ogG5JJsKw6gmxr36MWD3qU91OBrbgTVUlY 0V1vkndaUoGiNYqpenlHBiftihr7M+/oK63CVpAwuiwjDuOrtoGOQRy+RrSCnop2BeYR ucqQ== X-Received: by 10.236.99.38 with SMTP id w26mr26325011yhf.18.1394233869138; Fri, 07 Mar 2014 15:11:09 -0800 (PST) Received: from localhost.localdomain ([177.132.70.215]) by mx.google.com with ESMTPSA id h23sm32556000yhc.0.2014.03.07.15.11.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Mar 2014 15:11:08 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Mar 2014 20:10:22 -0300 Message-Id: <1394233836-3827-7-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1394233836-3827-1-git-send-email-przanoni@gmail.com> References: <1394233836-3827-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 06/20] drm/i915: properly clear IIR at irq_uninstall on Gen5+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni The IRQ_INIT and IRQ_FINI macros are basically the same thing, with the exception that IRQ_FINI doesn't properly clear IIR twice and doesn't have as many POSTING_READs as IRQ_INIT. So rename the macro to IRQ_RESET and use it everywhere. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 76 +++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f681462..73f1125 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -85,7 +85,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ * Also, make sure callers of these macros have something equivalent to a * POSTING_READ on the IIR register. * */ -#define GEN8_IRQ_INIT_NDX(type, which) do { \ +#define GEN8_IRQ_RESET_NDX(type, which) do { \ I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ POSTING_READ(GEN8_##type##_IMR(which)); \ I915_WRITE(GEN8_##type##_IER(which), 0); \ @@ -94,7 +94,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ } while (0) -#define GEN5_IRQ_INIT(type) do { \ +#define GEN5_IRQ_RESET(type) do { \ I915_WRITE(type##IMR, 0xffffffff); \ POSTING_READ(type##IMR); \ I915_WRITE(type##IER, 0); \ @@ -103,12 +103,6 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ I915_WRITE(type##IIR, 0xffffffff); \ } while (0) -#define GEN5_IRQ_FINI(type) do { \ - I915_WRITE(type##IMR, 0xffffffff); \ - I915_WRITE(type##IER, 0); \ - I915_WRITE(type##IIR, I915_READ(type##IIR)); \ -} while (0) - /* For display hotplug interrupt */ static void ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) @@ -2794,7 +2788,7 @@ static void ibx_irq_preinstall(struct drm_device *dev) if (HAS_PCH_NOP(dev)) return; - GEN5_IRQ_INIT(SDE); + GEN5_IRQ_RESET(SDE); /* * SDEIER is also touched by the interrupt handler to work around missed * PCH interrupts. Hence we can't update it after the interrupt handler @@ -2809,9 +2803,9 @@ static void gen5_gt_irq_preinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - GEN5_IRQ_INIT(GT); + GEN5_IRQ_RESET(GT); if (INTEL_INFO(dev)->gen >= 6) - GEN5_IRQ_INIT(GEN6_PM); + GEN5_IRQ_RESET(GEN6_PM); POSTING_READ(GTIIR); } @@ -2823,7 +2817,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev) I915_WRITE(HWSTAM, 0xeffe); - GEN5_IRQ_INIT(DE); + GEN5_IRQ_RESET(DE); gen5_gt_irq_preinstall(dev); @@ -2867,18 +2861,18 @@ static void gen8_irq_preinstall(struct drm_device *dev) I915_WRITE(GEN8_MASTER_IRQ, 0); POSTING_READ(GEN8_MASTER_IRQ); - GEN8_IRQ_INIT_NDX(GT, 0); - GEN8_IRQ_INIT_NDX(GT, 1); - GEN8_IRQ_INIT_NDX(GT, 2); - GEN8_IRQ_INIT_NDX(GT, 3); + GEN8_IRQ_RESET_NDX(GT, 0); + GEN8_IRQ_RESET_NDX(GT, 1); + GEN8_IRQ_RESET_NDX(GT, 2); + GEN8_IRQ_RESET_NDX(GT, 3); for_each_pipe(pipe) { - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); } - GEN5_IRQ_INIT(GEN8_DE_PORT_); - GEN5_IRQ_INIT(GEN8_DE_MISC_); - GEN5_IRQ_INIT(GEN8_PCU_); + GEN5_IRQ_RESET(GEN8_DE_PORT_); + GEN5_IRQ_RESET(GEN8_DE_MISC_); + GEN5_IRQ_RESET(GEN8_PCU_); POSTING_READ(GEN8_PCU_IIR); ibx_irq_preinstall(dev); @@ -3237,32 +3231,17 @@ static void gen8_irq_uninstall(struct drm_device *dev) I915_WRITE(GEN8_MASTER_IRQ, 0); -#define GEN8_IRQ_FINI_NDX(type, which) do { \ - I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ - I915_WRITE(GEN8_##type##_IER(which), 0); \ - I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ - } while (0) - -#define GEN8_IRQ_FINI(type) do { \ - I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ - I915_WRITE(GEN8_##type##_IER, 0); \ - I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ - } while (0) + GEN8_IRQ_RESET_NDX(GT, 0); + GEN8_IRQ_RESET_NDX(GT, 1); + GEN8_IRQ_RESET_NDX(GT, 2); + GEN8_IRQ_RESET_NDX(GT, 3); - GEN8_IRQ_FINI_NDX(GT, 0); - GEN8_IRQ_FINI_NDX(GT, 1); - GEN8_IRQ_FINI_NDX(GT, 2); - GEN8_IRQ_FINI_NDX(GT, 3); - - for_each_pipe(pipe) { - GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); - } + for_each_pipe(pipe) + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); - GEN8_IRQ_FINI(DE_PORT); - GEN8_IRQ_FINI(DE_MISC); - GEN8_IRQ_FINI(PCU); -#undef GEN8_IRQ_FINI -#undef GEN8_IRQ_FINI_NDX + GEN5_IRQ_RESET(GEN8_DE_PORT_); + GEN5_IRQ_RESET(GEN8_DE_MISC_); + GEN5_IRQ_RESET(GEN8_PCU_); POSTING_READ(GEN8_PCU_IIR); } @@ -3309,18 +3288,19 @@ static void ironlake_irq_uninstall(struct drm_device *dev) I915_WRITE(HWSTAM, 0xffffffff); - GEN5_IRQ_FINI(DE); + GEN5_IRQ_RESET(DE); if (IS_GEN7(dev)) I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); - GEN5_IRQ_FINI(GT); + GEN5_IRQ_RESET(GT); if (INTEL_INFO(dev)->gen >= 6) - GEN5_IRQ_FINI(GEN6_PM); + GEN5_IRQ_RESET(GEN6_PM); + POSTING_READ(GTIIR); if (HAS_PCH_NOP(dev)) return; - GEN5_IRQ_FINI(SDE); + GEN5_IRQ_RESET(SDE); if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) I915_WRITE(SERR_INT, I915_READ(SERR_INT)); }