From patchwork Fri Mar 7 23:10:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3795421 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3F4BA9F1CD for ; Fri, 7 Mar 2014 23:11:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4D897202EA for ; Fri, 7 Mar 2014 23:11:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 674E8202E9 for ; Fri, 7 Mar 2014 23:11:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5329FFB669; Fri, 7 Mar 2014 15:11:50 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f46.google.com (mail-yh0-f46.google.com [209.85.213.46]) by gabe.freedesktop.org (Postfix) with ESMTP id BD8EDFAD7A for ; Fri, 7 Mar 2014 15:11:10 -0800 (PST) Received: by mail-yh0-f46.google.com with SMTP id b6so2028061yha.5 for ; Fri, 07 Mar 2014 15:11:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FuSl6zptyOnGjg1U0wNlB7EgHylbjFPKujM8+6uSFk0=; b=XTeEmSSep8afJwCEm6SfnMB0uuXp8NrJjshB8spMNpYeriX8XciS/cCOQ6lbLCfbcj JuhdiZJ3rqiRe+AQ+DDFCivmkhwlqF7WcyOGng9g207wtqOQoVumrmi8AvmbwumVjVVw V2tRgLjyFpTP15DZKhiJDVICkvHNAhF8zl2F/GkwK1S7stXHgcGgsPKLffYPrOyNmW3g R3MEW2lTPDcFZlm+zMMEOQKNXHioiX3Z3KDSB8PFUp8K4h14d8oRb4YIGjZVKugSGmLz ktgdwgHEJVb6I6NGqLZsI+hJ+89OWw0KkmpIjxR3w5OcQwyvV8t5S3Kmx6OlmU8hSRm1 kPTA== X-Received: by 10.236.101.227 with SMTP id b63mr25276682yhg.37.1394233870475; Fri, 07 Mar 2014 15:11:10 -0800 (PST) Received: from localhost.localdomain ([177.132.70.215]) by mx.google.com with ESMTPSA id h23sm32556000yhc.0.2014.03.07.15.11.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Mar 2014 15:11:10 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Mar 2014 20:10:23 -0300 Message-Id: <1394233836-3827-8-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1394233836-3827-1-git-send-email-przanoni@gmail.com> References: <1394233836-3827-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 07/20] drm/i915: add GEN5_IRQ_INIT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni And the equivalent GEN8_IRQ_INIT_NDX macro. These macros are for the postinstall functions. The next patch will improve this macro. Notice that I could have included POSTING_READ calls to the macro, but that would mean the code would do a few more POSTING_READs than necessary. OTOH it would be more fail-proof. I can change that if needed. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 73f1125..6d4daf2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -103,6 +103,16 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ I915_WRITE(type##IIR, 0xffffffff); \ } while (0) +#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ + I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ + I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ +} while (0) + +#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ + I915_WRITE(type##IMR, (imr_val)); \ + I915_WRITE(type##IER, (ier_val)); \ +} while (0) + /* For display hotplug interrupt */ static void ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) @@ -2957,9 +2967,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) } I915_WRITE(GTIIR, I915_READ(GTIIR)); - I915_WRITE(GTIMR, dev_priv->gt_irq_mask); - I915_WRITE(GTIER, gt_irqs); - POSTING_READ(GTIER); + GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); if (INTEL_INFO(dev)->gen >= 6) { pm_irqs |= GEN6_PM_RPS_EVENTS; @@ -2969,10 +2977,9 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) dev_priv->pm_irq_mask = 0xffffffff; I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); - I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); - I915_WRITE(GEN6_PMIER, pm_irqs); - POSTING_READ(GEN6_PMIER); + GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); } + POSTING_READ(GTIER); } static int ironlake_irq_postinstall(struct drm_device *dev) @@ -3005,9 +3012,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) /* should always can generate irq */ I915_WRITE(DEIIR, I915_READ(DEIIR)); - I915_WRITE(DEIMR, dev_priv->irq_mask); - I915_WRITE(DEIER, display_mask | extra_mask); - POSTING_READ(DEIER); + GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); gen5_gt_irq_postinstall(dev); @@ -3172,8 +3177,7 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) if (tmp) DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", i, tmp); - I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); - I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); + GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); } POSTING_READ(GEN8_GT_IER(0)); } @@ -3196,13 +3200,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (tmp) DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", pipe, tmp); - I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); - I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); + GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], + de_pipe_enables); } POSTING_READ(GEN8_DE_PIPE_ISR(0)); - I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); - I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); + GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); POSTING_READ(GEN8_DE_PORT_IER); }