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[5/6] drm/i915: BDW needs D_COMP writes through MCHBAR

Message ID 1394233957-3904-6-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni March 7, 2014, 11:12 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

That's what the spec said! And HSW needs it through pcode (you can
only read it through MCHBAR), so create hsw_write_dcomp to abstract
the weirdness.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

Comments

Imre Deak April 1, 2014, 3:49 p.m. UTC | #1 
On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> That's what the spec said! And HSW needs it through pcode (you can
> only read it through MCHBAR), so create hsw_write_dcomp to abstract
> the weirdness.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++----------
>  1 file changed, 18 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d6092be..2be4129 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6664,6 +6664,22 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>  }
>  
> +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +
> +	if (IS_HASWELL(dev)) {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
> +					    val))
> +			DRM_ERROR("Failed to disable D_COMP\n");
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else {
> +		I915_WRITE(D_COMP, val);
> +	}
> +	POSTING_READ(D_COMP);
> +}
> +
>  /*
>   * This function implements pieces of two sequences from BSpec:
>   * - Sequence for display software to disable LCPLL
> @@ -6701,11 +6717,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
>  
>  	val = I915_READ(D_COMP);
>  	val |= D_COMP_COMP_DISABLE;
> -	mutex_lock(&dev_priv->rps.hw_lock);
> -	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
> -		DRM_ERROR("Failed to disable D_COMP\n");
> -	mutex_unlock(&dev_priv->rps.hw_lock);
> -	POSTING_READ(D_COMP);
> +	hsw_write_dcomp(dev_priv, val);
>  	ndelay(100);
>  
>  	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
> @@ -6760,11 +6772,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
>  	val = I915_READ(D_COMP);
>  	val |= D_COMP_COMP_FORCE;
>  	val &= ~D_COMP_COMP_DISABLE;
> -	mutex_lock(&dev_priv->rps.hw_lock);
> -	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
> -		DRM_ERROR("Failed to enable D_COMP\n");
> -	mutex_unlock(&dev_priv->rps.hw_lock);
> -	POSTING_READ(D_COMP);
> +	hsw_write_dcomp(dev_priv, val);
>  
>  	val = I915_READ(LCPLL_CTL);
>  	val &= ~LCPLL_PLL_DISABLE;
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6092be..2be4129 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6664,6 +6664,22 @@  static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	if (IS_HASWELL(dev)) {
+		mutex_lock(&dev_priv->rps.hw_lock);
+		if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
+					    val))
+			DRM_ERROR("Failed to disable D_COMP\n");
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else {
+		I915_WRITE(D_COMP, val);
+	}
+	POSTING_READ(D_COMP);
+}
+
 /*
  * This function implements pieces of two sequences from BSpec:
  * - Sequence for display software to disable LCPLL
@@ -6701,11 +6717,7 @@  static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 
 	val = I915_READ(D_COMP);
 	val |= D_COMP_COMP_DISABLE;
-	mutex_lock(&dev_priv->rps.hw_lock);
-	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
-		DRM_ERROR("Failed to disable D_COMP\n");
-	mutex_unlock(&dev_priv->rps.hw_lock);
-	POSTING_READ(D_COMP);
+	hsw_write_dcomp(dev_priv, val);
 	ndelay(100);
 
 	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
@@ -6760,11 +6772,7 @@  static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
 	val = I915_READ(D_COMP);
 	val |= D_COMP_COMP_FORCE;
 	val &= ~D_COMP_COMP_DISABLE;
-	mutex_lock(&dev_priv->rps.hw_lock);
-	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
-		DRM_ERROR("Failed to enable D_COMP\n");
-	mutex_unlock(&dev_priv->rps.hw_lock);
-	POSTING_READ(D_COMP);
+	hsw_write_dcomp(dev_priv, val);
 
 	val = I915_READ(LCPLL_CTL);
 	val &= ~LCPLL_PLL_DISABLE;