From patchwork Sat Mar 8 08:21:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 3797451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 66B24BF540 for ; Sat, 8 Mar 2014 08:21:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 707C92034E for ; Sat, 8 Mar 2014 08:21:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 60DAE2034C for ; Sat, 8 Mar 2014 08:21:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AEC1F9C39; Sat, 8 Mar 2014 00:21:33 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C090FAEB0 for ; Sat, 8 Mar 2014 00:20:32 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 08 Mar 2014 00:20:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,613,1389772800"; d="scan'208";a="488384368" Received: from sagar-desktop.iind.intel.com ([10.223.82.31]) by fmsmga001.fm.intel.com with ESMTP; 08 Mar 2014 00:20:30 -0800 From: sagar.a.kamble@intel.com To: intel-gfx@lists.freedesktop.org Date: Sat, 8 Mar 2014 13:51:18 +0530 Message-Id: <1394266879-20522-4-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.8.5 In-Reply-To: <1394266879-20522-1-git-send-email-sagar.a.kamble@intel.com> References: <1394266879-20522-1-git-send-email-sagar.a.kamble@intel.com> Cc: David Airlie , Daniel Vetter , Sagar Kamble , "Srinivas, Vidya" Subject: [Intel-gfx] [PATCH 3/4] drm/i915: Enabling pre-multiplied alpha drm property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sagar Kamble This patch enables property for changin the pixel format of plane to enable/disable pre-multiplied alpha format. Client has to set BIT(DRM_BLEND_PREMULTIPLIED_ALPHA) | 0x0/0x1 to disable/enable pre-multiplied alpha format. Cc: Daniel Vetter Cc: Jani Nikula Cc: David Airlie Signed-off-by: Srinivas, Vidya Signed-off-by: Sagar Kamble --- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_sprite.c | 73 ++++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index e33124c..44c366d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -685,6 +685,7 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, enum pipe pipe); void intel_wait_for_vblank(struct drm_device *dev, int pipe); +u32 control_premultiplied_alpha(u32 pixformat, unsigned int alpha); void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); void vlv_wait_port_ready(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 4c3d2a2..183bd80 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -120,6 +120,10 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, I915_WRITE(sprconstalpha, (blend_factor & SPRITE_CONSTANT_ALPHA_MASK) | SPRITE_CONSTANT_ALPHA_ENABLE); break; + case DRM_BLEND_PREMULTIPLIED_ALPHA: + sprctl |= control_premultiplied_alpha(sprctl & SP_PIXFORMAT_MASK, + blend_factor); + break; default: DRM_DEBUG_DRIVER("%x Blending operation not supported", intel_plane->blend_param.details.type); break; @@ -249,6 +253,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct intel_plane *intel_plane = to_intel_plane(plane); int pipe = intel_plane->pipe; u32 sprctl, sprscale = 0; + unsigned int blend_type, blend_factor; unsigned long sprsurf_offset, linear_offset; int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); @@ -283,6 +288,22 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, BUG(); } + /* Handle plane alpha and color blending properties */ + blend_type = intel_plane->blend_param.details.type; + blend_factor = intel_plane->blend_param.details.factor; + + switch (blend_type) { + case DRM_BLEND_NONE: + break; + case DRM_BLEND_PREMULTIPLIED_ALPHA: + sprctl |= control_premultiplied_alpha(sprctl & SPRITE_PIXFORMAT_MASK, + blend_factor); + break; + default: + DRM_DEBUG_DRIVER("%x Blending operation not supported", intel_plane->blend_param.details.type); + break; + } + /* * Enable gamma to match primary/cursor plane behaviour. * FIXME should be user controllable via propertiesa. @@ -434,6 +455,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, int pipe = intel_plane->pipe; unsigned long dvssurf_offset, linear_offset; u32 dvscntr, dvsscale; + unsigned int blend_type, blend_factor; int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); dvscntr = I915_READ(DVSCNTR(pipe)); @@ -467,6 +489,22 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, BUG(); } + /* Handle plane alpha and color blending properties */ + blend_type = intel_plane->blend_param.details.type; + blend_factor = intel_plane->blend_param.details.factor; + + switch (blend_type) { + case DRM_BLEND_NONE: + break; + case DRM_BLEND_PREMULTIPLIED_ALPHA: + dvscntr |= control_premultiplied_alpha(dvscntr & DVS_PIXFORMAT_MASK, + blend_factor); + break; + default: + DRM_DEBUG_DRIVER("%x Blending operation not supported", intel_plane->blend_param.details.type); + break; + } + /* * Enable gamma to match primary/cursor plane behaviour. * FIXME should be user controllable via propertiesa. @@ -1112,6 +1150,38 @@ static uint32_t vlv_plane_formats[] = { DRM_FORMAT_VYUY, }; +u32 control_premultiplied_alpha(u32 pixformat, unsigned int alpha) +{ + switch (pixformat) { + case DISPPLANE_RGBX888: + case DISPPLANE_RGBA888: + if (alpha) + pixformat = DISPPLANE_RGBA888; + else + pixformat = DISPPLANE_RGBX888; + break; + case DISPPLANE_BGRX888: + case DISPPLANE_BGRA888: + if (alpha) + pixformat = DISPPLANE_BGRA888; + else + pixformat = DISPPLANE_BGRX888; + break; + case DISPPLANE_RGBX101010: + case DISPPLANE_RGBA101010: + if (alpha) + pixformat = DISPPLANE_RGBA101010; + else + pixformat = DISPPLANE_RGBX101010; + break; + default: + if (alpha) + DRM_DEBUG_DRIVER("Pixel format 0x%08x does not support Alpha Control\n", pixformat); + break; + } + return pixformat; +} + int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) { @@ -1201,7 +1271,8 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) if (!dev_priv->blend_property) dev_priv->blend_property = drm_mode_create_blend_property(dev, BIT(DRM_BLEND_NONE) | - BIT(DRM_BLEND_CONSTANT_ALPHA)); + BIT(DRM_BLEND_CONSTANT_ALPHA) | + BIT(DRM_BLEND_PREMULTIPLIED_ALPHA)); if (dev_priv->blend_property) drm_object_attach_property(&intel_plane->base.base,