| Message ID | 1394726418-10831-2-git-send-email-deepak.s@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Mar 13, 2014 at 09:30:16PM +0530, deepak.s@linux.intel.com wrote: > From: Deepak S <deepak.s@intel.com> > > When we use different rps events for different platform or due to wa, we > mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable > in dev_priv to track the enabled PM interrupts > > Signed-off-by: Deepak S <deepak.s@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_irq.c | 14 +++++++------- > drivers/gpu/drm/i915/intel_pm.c | 14 +++++++++----- > 3 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 70fbe90..d522313 100644 <snip> > @@ -3311,6 +3311,8 @@ static void gen8_enable_rps(struct drm_device *dev) > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_AVG); > > + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; > + > /* 6: Ring frequency + overclocking (our driver does this later */ > > gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); > @@ -3430,6 +3432,7 @@ static void gen6_enable_rps(struct drm_device *dev) > dev_priv->rps.power = HIGH_POWER; /* force a reset */ > gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > > + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; > gen6_enable_rps_interrupts(dev); > > rc6vids = 0; > @@ -3688,6 +3691,7 @@ static void valleyview_enable_rps(struct drm_device *dev) > dev_priv->rps.rp_up_masked = false; > dev_priv->rps.rp_down_masked = false; > > + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; > gen6_enable_rps_interrupts(dev); > > gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); I think we need to initialize pm_rps_events somewhere earlier since we depend on it already in irq postinstall. Othwewise the patch looks good.
On 3/13/2014 11:46 PM, Ville Syrjälä wrote: > On Thu, Mar 13, 2014 at 09:30:16PM +0530, deepak.s@linux.intel.com wrote: >> From: Deepak S <deepak.s@intel.com> >> >> When we use different rps events for different platform or due to wa, we >> mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable >> in dev_priv to track the enabled PM interrupts >> >> Signed-off-by: Deepak S <deepak.s@linux.intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/i915_irq.c | 14 +++++++------- >> drivers/gpu/drm/i915/intel_pm.c | 14 +++++++++----- >> 3 files changed, 17 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 70fbe90..d522313 100644 > <snip> >> @@ -3311,6 +3311,8 @@ static void gen8_enable_rps(struct drm_device *dev) >> GEN6_RP_UP_BUSY_AVG | >> GEN6_RP_DOWN_IDLE_AVG); >> >> + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; >> + >> /* 6: Ring frequency + overclocking (our driver does this later */ >> >> gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); >> @@ -3430,6 +3432,7 @@ static void gen6_enable_rps(struct drm_device *dev) >> dev_priv->rps.power = HIGH_POWER; /* force a reset */ >> gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); >> >> + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; >> gen6_enable_rps_interrupts(dev); >> >> rc6vids = 0; >> @@ -3688,6 +3691,7 @@ static void valleyview_enable_rps(struct drm_device *dev) >> dev_priv->rps.rp_up_masked = false; >> dev_priv->rps.rp_down_masked = false; >> >> + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; >> gen6_enable_rps_interrupts(dev); >> >> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > > I think we need to initialize pm_rps_events somewhere earlier since we > depend on it already in irq postinstall. Othwewise the patch looks > good. Adding it in functions "intel_uncore_early_sanitize" or "pm_init" as this gets executed before irq_install in driver_load?
On Fri, Mar 14, 2014 at 12:13:30AM +0530, S, Deepak wrote: > > > On 3/13/2014 11:46 PM, Ville Syrjälä wrote: > > On Thu, Mar 13, 2014 at 09:30:16PM +0530, deepak.s@linux.intel.com wrote: > >> From: Deepak S <deepak.s@intel.com> > >> > >> When we use different rps events for different platform or due to wa, we > >> mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable > >> in dev_priv to track the enabled PM interrupts > >> > >> Signed-off-by: Deepak S <deepak.s@linux.intel.com> > >> --- > >> drivers/gpu/drm/i915/i915_drv.h | 1 + > >> drivers/gpu/drm/i915/i915_irq.c | 14 +++++++------- > >> drivers/gpu/drm/i915/intel_pm.c | 14 +++++++++----- > >> 3 files changed, 17 insertions(+), 12 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >> index 70fbe90..d522313 100644 > > <snip> > >> @@ -3311,6 +3311,8 @@ static void gen8_enable_rps(struct drm_device *dev) > >> GEN6_RP_UP_BUSY_AVG | > >> GEN6_RP_DOWN_IDLE_AVG); > >> > >> + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; > >> + > >> /* 6: Ring frequency + overclocking (our driver does this later */ > >> > >> gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); > >> @@ -3430,6 +3432,7 @@ static void gen6_enable_rps(struct drm_device *dev) > >> dev_priv->rps.power = HIGH_POWER; /* force a reset */ > >> gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > >> > >> + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; > >> gen6_enable_rps_interrupts(dev); > >> > >> rc6vids = 0; > >> @@ -3688,6 +3691,7 @@ static void valleyview_enable_rps(struct drm_device *dev) > >> dev_priv->rps.rp_up_masked = false; > >> dev_priv->rps.rp_down_masked = false; > >> > >> + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; > >> gen6_enable_rps_interrupts(dev); > >> > >> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > > > > I think we need to initialize pm_rps_events somewhere earlier since we > > depend on it already in irq postinstall. Othwewise the patch looks > > good. > Adding it in functions "intel_uncore_early_sanitize" or "pm_init" as > this gets executed before irq_install in driver_load? intel_irq_init() might be a good choice since that's where we also initialize the rps.work, and then it's clear it gets executed before any other irq setup code.
From: Deepak S <deepak.s@linux.intel.com>
This series adds WA patches to enable RC6 and Turbo to work together and also adds a patch to contol the rps boost at runtime
Deepak S (3):
drm/i915: Track the enabled PM interrupts in dev_priv.
drm/i915/vlv: WA for Turbo and RC6 to work together.
drm/i915: Add boot paramter to control rps boost at boot time.
drivers/gpu/drm/i915/i915_drv.h | 17 +++++
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 141 +++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_params.c | 5 ++
drivers/gpu/drm/i915/i915_reg.h | 13 +++-
drivers/gpu/drm/i915/intel_pm.c | 26 ++++---
6 files changed, 186 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 70fbe90..d522313 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1487,6 +1487,7 @@ typedef struct drm_i915_private { }; u32 gt_irq_mask; u32 pm_irq_mask; + u32 pm_rps_events; u32 pipestat_irq_mask[I915_MAX_PIPES]; struct work_struct hotplug_work; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 37f852d..04f2742 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1132,13 +1132,13 @@ static void gen6_pm_rps_work(struct work_struct *work) pm_iir = dev_priv->rps.pm_iir; dev_priv->rps.pm_iir = 0; /* Make sure not to corrupt PMIMR state used by ringbuffer code */ - snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); + snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); spin_unlock_irq(&dev_priv->irq_lock); /* Make sure we didn't queue anything we're not going to process. */ - WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); + WARN_ON(pm_iir & ~dev_priv->pm_rps_events); - if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) + if ((pm_iir & dev_priv->pm_rps_events) == 0) return; mutex_lock(&dev_priv->rps.hw_lock); @@ -1555,10 +1555,10 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) * the work queue. */ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) { - if (pm_iir & GEN6_PM_RPS_EVENTS) { + if (pm_iir & dev_priv->pm_rps_events) { spin_lock(&dev_priv->irq_lock); - dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; - snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); + dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; + snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); spin_unlock(&dev_priv->irq_lock); queue_work(dev_priv->wq, &dev_priv->rps.work); @@ -2983,7 +2983,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) POSTING_READ(GTIER); if (INTEL_INFO(dev)->gen >= 6) { - pm_irqs |= GEN6_PM_RPS_EVENTS; + pm_irqs |= dev_priv->pm_rps_events; if (HAS_VEBOX(dev)) pm_irqs |= PM_VEBOX_USER_INTERRUPT; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ad58ce3..bf6baa6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3160,7 +3160,7 @@ static void gen6_disable_rps_interrupts(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); - I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS); + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~dev_priv->pm_rps_events); /* Complete PM interrupt masking here doesn't race with the rps work * item again unmasking PM interrupts because that is using a different * register (PMIMR) to mask PM interrupts. The only risk is in leaving @@ -3170,7 +3170,7 @@ static void gen6_disable_rps_interrupts(struct drm_device *dev) dev_priv->rps.pm_iir = 0; spin_unlock_irq(&dev_priv->irq_lock); - I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); + I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); } static void gen6_disable_rps(struct drm_device *dev) @@ -3232,12 +3232,12 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) spin_lock_irq(&dev_priv->irq_lock); WARN_ON(dev_priv->rps.pm_iir); - snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); - I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); + snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); + I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); spin_unlock_irq(&dev_priv->irq_lock); /* only unmask PM interrupts we need. Mask all others. */ - enabled_intrs = GEN6_PM_RPS_EVENTS; + enabled_intrs = dev_priv->pm_rps_events; /* IVB and SNB hard hangs on looping batchbuffer * if GEN6_PM_UP_EI_EXPIRED is masked. @@ -3311,6 +3311,8 @@ static void gen8_enable_rps(struct drm_device *dev) GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; + /* 6: Ring frequency + overclocking (our driver does this later */ gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); @@ -3430,6 +3432,7 @@ static void gen6_enable_rps(struct drm_device *dev) dev_priv->rps.power = HIGH_POWER; /* force a reset */ gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; gen6_enable_rps_interrupts(dev); rc6vids = 0; @@ -3688,6 +3691,7 @@ static void valleyview_enable_rps(struct drm_device *dev) dev_priv->rps.rp_up_masked = false; dev_priv->rps.rp_down_masked = false; + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; gen6_enable_rps_interrupts(dev); gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);