From patchwork Tue Mar 18 14:18:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 3848321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C0EABBF540 for ; Tue, 18 Mar 2014 14:19:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C094120260 for ; Tue, 18 Mar 2014 14:19:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8F9AD20256 for ; Tue, 18 Mar 2014 14:19:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 37AEC8D77B; Tue, 18 Mar 2014 07:19:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com [209.85.220.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 024DC8D77A for ; Tue, 18 Mar 2014 07:19:22 -0700 (PDT) Received: by mail-pa0-f43.google.com with SMTP id bj1so7381390pad.2 for ; Tue, 18 Mar 2014 07:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RuOwYZAeGsP+/swQrQewtLAS4g6+2qFfP6mT1cMync4=; b=ulzyDqz71cee40o0eCyMSCbYnFm4qXKpeBgFfF9XGhHwYmXzOXsnqaZdrObTYGeDAs nOA0sB8/J6vDJTFb9wjK/5sSNTL0NEUSOMfuwXh0C9srXusrOXy1RmpwVVZsVV/2Es+t /119C+324YHaHYqe7AC1aUpc1jkLiAXM7F2yV7BNPsO11j4yfNGJ9Spzg4BNcAA5J1gk c08OPfm/imF9LZZ+i64fHRO+n+NJkDPgFzqWNXhvKc0duGIhaWUg6eo3GDJoOoQVivvX hyfsmzctv8/dBR6MgJbu5WuTSUJ5SBa2mqJw1OH7N5WCipxXsZtbvsjpmhYpnwh/LOGG goDw== X-Received: by 10.66.141.144 with SMTP id ro16mr11276473pab.131.1395152362580; Tue, 18 Mar 2014 07:19:22 -0700 (PDT) Received: from localhost (jfdmzpr05-ext.jf.intel.com. [134.134.139.74]) by mx.google.com with ESMTPSA id yv7sm88520679pac.33.2014.03.18.07.19.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Mar 2014 07:19:21 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Mar 2014 11:18:56 -0300 Message-Id: <1395152336-7914-4-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1395152336-7914-1-git-send-email-rodrigo.vivi@gmail.com> References: <1395152336-7914-1-git-send-email-rodrigo.vivi@gmail.com> Cc: , ChrisWilsonchris@chris-wilson.co.uk Subject: [Intel-gfx] [PATCH 4/4] tests/gem_gtt_hog: Fix for BDW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update XY_COLOR_BLT command for Broadwell. v2: stash devid and remove ugly double allocation. (by Chris). v3: fix inverted blt command size and stash fd, devid and intel_gen. v4: improved len calculation and noop between blt commands. (by Chris). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=73724 Cc: Chris Wilson chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi --- tests/gem_gtt_hog.c | 52 +++++++++++++++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/tests/gem_gtt_hog.c b/tests/gem_gtt_hog.c index d22e074..c7206dc 100644 --- a/tests/gem_gtt_hog.c +++ b/tests/gem_gtt_hog.c @@ -44,20 +44,26 @@ static const uint32_t canary = 0xdeadbeef; +typedef struct data { + int fd; + int devid; + int intel_gen; +} data_t; + static double elapsed(const struct timeval *start, const struct timeval *end) { return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec); } -static void busy(int fd, uint32_t handle, int size, int loops) +static void busy(data_t *data, uint32_t handle, int size, int loops) { struct drm_i915_gem_relocation_entry reloc[20]; struct drm_i915_gem_exec_object2 gem_exec[2]; struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_pwrite gem_pwrite; struct drm_i915_gem_create create; - uint32_t buf[122], *b; + uint32_t buf[170], *b; int i; memset(reloc, 0, sizeof(reloc)); @@ -66,7 +72,8 @@ static void busy(int fd, uint32_t handle, int size, int loops) b = buf; for (i = 0; i < 20; i++) { - *b++ = XY_COLOR_BLT_CMD_NOLEN | 4 | + *b++ = XY_COLOR_BLT_CMD_NOLEN | + ((data->intel_gen >= 8) ? 5 : 4) | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB; *b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096; *b++ = 0; @@ -76,66 +83,68 @@ static void busy(int fd, uint32_t handle, int size, int loops) reloc[i].read_domains = I915_GEM_DOMAIN_RENDER; reloc[i].write_domain = I915_GEM_DOMAIN_RENDER; *b++ = 0; + if (data->intel_gen >= 8) + *b++ = 0; *b++ = canary; } *b++ = MI_BATCH_BUFFER_END; - *b++ = 0; + if ((b - buf) & 1) + *b++ = 0; gem_exec[0].handle = handle; gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE; create.handle = 0; create.size = 4096; - drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + drmIoctl(data->fd, DRM_IOCTL_I915_GEM_CREATE, &create); gem_exec[1].handle = create.handle; gem_exec[1].relocation_count = 20; gem_exec[1].relocs_ptr = (uintptr_t)reloc; execbuf.buffers_ptr = (uintptr_t)gem_exec; execbuf.buffer_count = 2; - execbuf.batch_len = sizeof(buf); + execbuf.batch_len = (b - buf) * sizeof(buf[0]); execbuf.flags = 1 << 11; - if (HAS_BLT_RING(intel_get_drm_devid(fd))) + if (HAS_BLT_RING(data->devid)) execbuf.flags |= I915_EXEC_BLT; gem_pwrite.handle = gem_exec[1].handle; gem_pwrite.offset = 0; - gem_pwrite.size = sizeof(buf); + gem_pwrite.size = execbuf.batch_len; gem_pwrite.data_ptr = (uintptr_t)buf; - if (drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) { + if (drmIoctl(data->fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) { while (loops--) - drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); + drmIoctl(data->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); } - drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &create.handle); + drmIoctl(data->fd, DRM_IOCTL_GEM_CLOSE, &create.handle); } -static void run(int child) +static void run(data_t *data, int child) { const int size = 4096 * (256 + child * child); const int tiling = child % 2; const int write = child % 2; - int fd = drm_open_any(); - uint32_t handle = gem_create(fd, size); + uint32_t handle = gem_create(data->fd, size); uint32_t *ptr; uint32_t x; igt_assert(handle); if (tiling != I915_TILING_NONE) - gem_set_tiling(fd, handle, tiling, 4096); + gem_set_tiling(data->fd, handle, tiling, 4096); /* load up the unfaulted bo */ - busy(fd, handle, size, 100); + busy(data, handle, size, 100); /* Note that we ignore the API and rely on the implict * set-to-gtt-domain within the fault handler. */ if (write) { - ptr = gem_mmap(fd, handle, size, PROT_READ | PROT_WRITE); + ptr = gem_mmap(data->fd, handle, size, PROT_READ | PROT_WRITE); ptr[rand() % (size / 4)] = canary; } else - ptr = gem_mmap(fd, handle, size, PROT_READ); + ptr = gem_mmap(data->fd, handle, size, PROT_READ); x = ptr[rand() % (size / 4)]; munmap(ptr, size); @@ -147,6 +156,7 @@ igt_simple_main { struct timeval start, end; pid_t children[64]; + data_t data = {}; int n; /* check for an intel gpu before goint nuts. */ @@ -155,11 +165,15 @@ igt_simple_main igt_skip_on_simulation(); + data.fd = drm_open_any(); + data.devid = intel_get_drm_devid(data.fd); + data.intel_gen = intel_gen(data.devid); + gettimeofday(&start, NULL); for (n = 0; n < ARRAY_SIZE(children); n++) { switch ((children[n] = fork())) { case -1: igt_assert(0); - case 0: run(n); break; + case 0: run(&data, n); break; default: break; } }