From patchwork Thu Mar 20 01:31:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3862601 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8EA7DBF540 for ; Thu, 20 Mar 2014 01:31:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F299020251 for ; Thu, 20 Mar 2014 01:31:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 06FA6202B8 for ; Thu, 20 Mar 2014 01:31:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10B4D890BE; Wed, 19 Mar 2014 18:31:30 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FB8D890BF for ; Wed, 19 Mar 2014 18:31:29 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 19 Mar 2014 18:26:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,690,1389772800"; d="scan'208";a="476065968" Received: from ironside.jf.intel.com ([10.7.197.60]) by orsmga001.jf.intel.com with ESMTP; 19 Mar 2014 18:31:20 -0700 From: Ben Widawsky To: Intel GFX Date: Wed, 19 Mar 2014 18:31:12 -0700 Message-Id: <1395279079-12704-6-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1395279079-12704-1-git-send-email-benjamin.widawsky@intel.com> References: <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> <1395279079-12704-1-git-send-email-benjamin.widawsky@intel.com> Subject: [Intel-gfx] [PATCH 05/12] drm/i915: Remove extraneous MMIO for RPS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The values created at initialization must always exist to use the interface. Reading them again is confusing, and pointless. More cleanups are coming in the next patch. Since I am not 100% certain, moreover on BYT, (though I am extremely close to that) that there is no need to leave the MMIO here, I wanted to make it a separate patch for the bisectable 'just-in-case' Signed-off-by: Ben Widawsky Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_sysfs.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index e3fa8cd..49554d9 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -313,7 +313,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, struct drm_minor *minor = dev_to_drm_minor(kdev); struct drm_device *dev = minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 val, rp_state_cap, hw_max, hw_min, non_oc_max; + u32 val, hw_max, hw_min, non_oc_max; ssize_t ret; ret = kstrtou32(buf, 0, &val); @@ -327,16 +327,14 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, if (IS_VALLEYVIEW(dev_priv->dev)) { val = vlv_freq_opcode(dev_priv, val); - hw_max = valleyview_rps_max_freq(dev_priv); - hw_min = valleyview_rps_min_freq(dev_priv); - non_oc_max = hw_max; + non_oc_max = hw_max = dev_priv->rps.max_freq; + hw_min = dev_priv->rps.min_freq; } else { val /= GT_FREQUENCY_MULTIPLIER; - rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); hw_max = dev_priv->rps.max_freq; - non_oc_max = (rp_state_cap & 0xff); - hw_min = ((rp_state_cap & 0xff0000) >> 16); + non_oc_max = dev_priv->rps.rp0_freq; + hw_min = dev_priv->rps.min_freq; } if (val < hw_min || val > hw_max || @@ -394,7 +392,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, struct drm_minor *minor = dev_to_drm_minor(kdev); struct drm_device *dev = minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 val, rp_state_cap, hw_max, hw_min; + u32 val, hw_max, hw_min; ssize_t ret; ret = kstrtou32(buf, 0, &val); @@ -408,14 +406,13 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, if (IS_VALLEYVIEW(dev)) { val = vlv_freq_opcode(dev_priv, val); - hw_max = valleyview_rps_max_freq(dev_priv); - hw_min = valleyview_rps_min_freq(dev_priv); + hw_max = dev_priv->rps.max_freq; + hw_min = dev_priv->rps.min_freq; } else { val /= GT_FREQUENCY_MULTIPLIER; - rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); hw_max = dev_priv->rps.max_freq; - hw_min = ((rp_state_cap & 0xff0000) >> 16); + hw_min = dev_priv->rps.min_freq; } if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {