From patchwork Mon Mar 24 17:30:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 3883201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 970ACBF540 for ; Mon, 24 Mar 2014 17:29:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C045520263 for ; Mon, 24 Mar 2014 17:29:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E8CFD2020F for ; Mon, 24 Mar 2014 17:29:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 88B1C6EB2F; Mon, 24 Mar 2014 10:29:38 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id A0E2A6EB2F for ; Mon, 24 Mar 2014 10:29:37 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 24 Mar 2014 10:25:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,721,1389772800"; d="scan'208";a="478971092" Received: from sourabgu-desktop.iind.intel.com ([10.223.82.69]) by orsmga001.jf.intel.com with ESMTP; 24 Mar 2014 10:29:34 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Mar 2014 23:00:02 +0530 Message-Id: <1395682207-7092-2-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> Cc: Daniel Vetter , Akash Goel , Sourab Gupta Subject: [Intel-gfx] [PATCH v4 1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI Store data commands. v2: Modified the WA comment (Ville) v3: Added the vlv identifier with WA name (Damien) v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func, sending 6 dwords instead of 8) Signed-off-by: Sourab Gupta Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 87d1a2d..75cac4e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -309,6 +309,29 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + if (invalidate_domains && IS_VALLEYVIEW(ring->dev)) { + /* + * WaTlbInvalidateStoreDataBefore:vlv + * This workaround is applicable in case the flush call has + * arrived in context of invalidate_all_caches function. + * Before pipecontrol with TLB invalidate set, need 2 store + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) + * Without this, hardware cannot guarantee the command after the + * PIPE_CONTROL with TLB inv will not use the old TLB values. + * FIXME: should apply to snb, ivb + */ + int i; + ret = intel_ring_begin(ring, 3 * 2); + if (ret) + return ret; + for (i = 0; i < 2; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); + } + /* * Ensure that any following seqno writes only happen when the render * cache is indeed flushed.