From patchwork Tue Mar 25 09:53:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 3886471 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 49E7ABF540 for ; Tue, 25 Mar 2014 09:53:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6311F202DD for ; Tue, 25 Mar 2014 09:53:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7C1D6202B4 for ; Tue, 25 Mar 2014 09:53:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF6736E0F0; Tue, 25 Mar 2014 02:53:41 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 902F06E0F0 for ; Tue, 25 Mar 2014 02:53:40 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 25 Mar 2014 02:53:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,728,1389772800"; d="scan'208";a="506982990" Received: from sourabgu-desktop.iind.intel.com ([10.223.82.69]) by orsmga002.jf.intel.com with ESMTP; 25 Mar 2014 02:53:37 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 25 Mar 2014 15:23:34 +0530 Message-Id: <1395741214-26440-1-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <20140325091512.GZ4366@nuc-i3427.alporthouse.com> References: <20140325091512.GZ4366@nuc-i3427.alporthouse.com> Cc: Daniel Vetter , Akash Goel , Sourab Gupta Subject: [Intel-gfx] [PATCH v6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. This workaround has to be applied before doing TLB Invalidation on render ring. In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI Store data commands. Without this, hardware cannot guarantee the command after the PIPE_CONTROL with TLB inv will not use the old TLB values. v2: Modified the WA comment (Ville) v3: Added the vlv identifier with WA name (Damien) v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func, sending 6 dwords instead of 8) (Chris) v5: Enhancing the scope of WA to gen6, gen7. Having a common WA func being called from gen6, gen7 flush functions. (Ville) v6: WA is applicable only to render ring, earlier put for all rings in v5. (Chris) Signed-off-by: Sourab Gupta Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 87d1a2d..816137f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -208,6 +208,31 @@ intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) } static int +gen6_tlb_invalidate_wa(struct intel_ring_buffer *ring) +{ + /* + * WaTlbInvalidateStoreDataBefore:gen6,gen7 + * This workaround has to be applied before doing TLB invalidation + * on the render ring. Before pipecontrol with TLB invalidate set, + * need 2 store data commands (such as MI_STORE_DATA_IMM or + * MI_STORE_DATA_INDEX). Without this, hardware cannot guarantee + * the command after the PIPE_CONTROL with TLB inv will not use + * the old TLB values. + */ + int i, ret; + ret = intel_ring_begin(ring, 3 * 2); + if (ret) + return ret; + for (i = 0; i < 2; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); + return 0; +} + +static int gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) { @@ -215,6 +240,13 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate_domains) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + /* Force SNB workarounds for PIPE_CONTROL flushes */ ret = intel_emit_post_sync_nonzero_flush(ring); if (ret) @@ -309,6 +341,13 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate_domains) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + /* * Ensure that any following seqno writes only happen when the render * cache is indeed flushed.