From patchwork Thu Mar 27 17:59:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 3898911 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E1C8DBF540 for ; Thu, 27 Mar 2014 17:12:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0C03E20237 for ; Thu, 27 Mar 2014 17:12:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4EB8C20253 for ; Thu, 27 Mar 2014 17:12:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE2CC6EA1C; Thu, 27 Mar 2014 10:12:28 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 32F726EA21 for ; Thu, 27 Mar 2014 10:12:26 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 27 Mar 2014 10:07:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,743,1389772800"; d="scan'208";a="501086474" Received: from omateolo-linux2.iwi.intel.com ([172.28.253.148]) by fmsmga001.fm.intel.com with ESMTP; 27 Mar 2014 10:05:52 -0700 From: oscar.mateo@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 27 Mar 2014 17:59:42 +0000 Message-Id: <1395943218-7708-14-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1395943218-7708-1-git-send-email-oscar.mateo@intel.com> References: <1395943218-7708-1-git-send-email-oscar.mateo@intel.com> Subject: [Intel-gfx] [PATCH 13/49] drm/i915/bdw: Execlists ring tail writing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo The write tail function is a very special place for execlists: since all access to the ring is mediated through requests (thanks to Chris Wilson's "Write RING_TAIL once per-request" for that) and all requests end up with a write tail, this is the place we are going to use to submit contexts for execution. For the moment, just mark the place (we still need to do a lot of preparation before execlists are ready to start submitting things). Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_ringbuffer.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 35e022f..a18dcf7 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -413,6 +413,12 @@ static void ring_write_tail(struct intel_engine *ring, I915_WRITE_TAIL(ring, value); } +static void gen8_write_tail_lrc(struct intel_engine *ring, + u32 value) +{ + DRM_ERROR("Execlists still not ready!\n"); +} + u32 intel_ring_get_active_head(struct intel_engine *ring) { drm_i915_private_t *dev_priv = ring->dev->dev_private; @@ -1907,12 +1913,15 @@ int intel_init_render_ring(struct drm_device *dev) drm_i915_private_t *dev_priv = dev->dev_private; struct intel_engine *ring = &dev_priv->ring[RCS]; + ring->write_tail = ring_write_tail; if (INTEL_INFO(dev)->gen >= 6) { ring->add_request = gen6_add_request; ring->flush = gen7_render_ring_flush; if (INTEL_INFO(dev)->gen == 6) ring->flush = gen6_render_ring_flush; if (INTEL_INFO(dev)->gen >= 8) { + if (dev_priv->lrc_enabled) + ring->write_tail = gen8_write_tail_lrc; ring->flush = gen8_render_ring_flush; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; @@ -1958,7 +1967,7 @@ int intel_init_render_ring(struct drm_device *dev) } ring->irq_enable_mask = I915_USER_INTERRUPT; } - ring->write_tail = ring_write_tail; + if (IS_HASWELL(dev)) ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; else if (IS_GEN8(dev)) @@ -2079,6 +2088,8 @@ int intel_init_bsd_ring(struct drm_device *dev) ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { + if (dev_priv->lrc_enabled) + ring->write_tail = gen8_write_tail_lrc; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2133,6 +2144,8 @@ int intel_init_blt_ring(struct drm_device *dev) ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { + if (dev_priv->lrc_enabled) + ring->write_tail = gen8_write_tail_lrc; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2170,6 +2183,8 @@ int intel_init_vebox_ring(struct drm_device *dev) ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { + if (dev_priv->lrc_enabled) + ring->write_tail = gen8_write_tail_lrc; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq;