From patchwork Thu Mar 27 17:59:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 3898501 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0BC849F334 for ; Thu, 27 Mar 2014 17:08:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 20D1020253 for ; Thu, 27 Mar 2014 17:08:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EB1BD20240 for ; Thu, 27 Mar 2014 17:08:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95D096E9D8; Thu, 27 Mar 2014 10:08:05 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id BD1916E9D8 for ; Thu, 27 Mar 2014 10:08:04 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 27 Mar 2014 10:07:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,743,1389772800"; d="scan'208";a="501086481" Received: from omateolo-linux2.iwi.intel.com ([172.28.253.148]) by fmsmga001.fm.intel.com with ESMTP; 27 Mar 2014 10:05:53 -0700 From: oscar.mateo@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 27 Mar 2014 17:59:43 +0000 Message-Id: <1395943218-7708-15-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1395943218-7708-1-git-send-email-oscar.mateo@intel.com> References: <1395943218-7708-1-git-send-email-oscar.mateo@intel.com> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 14/49] drm/i915/bdw: LR context ring init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky Logical ring contexts do not need most of the ring init: we just need the pipe control object for the render ring and a few other things (some of which will be added later). Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_ringbuffer.c | 42 ++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a18dcf7..6e53ce1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -528,6 +528,18 @@ out: return ret; } +static int init_ring_common_lrc(struct intel_engine *ring) +{ + struct intel_ringbuffer *ringbuf = __get_ringbuf(ring); + + ringbuf->head = 0; + ringbuf->tail = 0; + ringbuf->space = ringbuf->size; + ringbuf->last_retired_head = -1; + + return 0; +} + static int init_pipe_control(struct intel_engine *ring) { @@ -630,6 +642,12 @@ static int init_render_ring(struct intel_engine *ring) return ret; } +static int init_render_ring_lrc(struct intel_engine *ring) +{ + init_ring_common_lrc(ring); + return init_pipe_control(ring); +} + static void render_ring_cleanup(struct intel_engine *ring) { struct drm_device *dev = ring->dev; @@ -1914,14 +1932,17 @@ int intel_init_render_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[RCS]; ring->write_tail = ring_write_tail; + ring->init = init_render_ring; if (INTEL_INFO(dev)->gen >= 6) { ring->add_request = gen6_add_request; ring->flush = gen7_render_ring_flush; if (INTEL_INFO(dev)->gen == 6) ring->flush = gen6_render_ring_flush; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_render_ring_lrc; + } ring->flush = gen8_render_ring_flush; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; @@ -1980,7 +2001,6 @@ int intel_init_render_ring(struct drm_device *dev) ring->dispatch_execbuffer = i830_dispatch_execbuffer; else ring->dispatch_execbuffer = i915_dispatch_execbuffer; - ring->init = init_render_ring; ring->cleanup = render_ring_cleanup; /* Workaround batchbuffer to combat CS tlb bug. */ @@ -2079,6 +2099,7 @@ int intel_init_bsd_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[VCS]; ring->write_tail = ring_write_tail; + ring->init = init_ring_common; if (INTEL_INFO(dev)->gen >= 6) { /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN6(dev)) @@ -2088,8 +2109,10 @@ int intel_init_bsd_ring(struct drm_device *dev) ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_ring_common_lrc; + } ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2128,7 +2151,6 @@ int intel_init_bsd_ring(struct drm_device *dev) } ring->dispatch_execbuffer = i965_dispatch_execbuffer; } - ring->init = init_ring_common; return intel_init_ring(dev, ring); } @@ -2139,13 +2161,16 @@ int intel_init_blt_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[BCS]; ring->write_tail = ring_write_tail; + ring->init = init_ring_common; ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_ring_common_lrc; + } ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2166,7 +2191,6 @@ int intel_init_blt_ring(struct drm_device *dev) ring->signal_mbox[VCS] = GEN6_VBSYNC; ring->signal_mbox[BCS] = GEN6_NOSYNC; ring->signal_mbox[VECS] = GEN6_VEBSYNC; - ring->init = init_ring_common; return intel_init_ring(dev, ring); } @@ -2177,14 +2201,17 @@ int intel_init_vebox_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[VECS]; ring->write_tail = ring_write_tail; + ring->init = init_ring_common; ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_ring_common_lrc; + } ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2205,7 +2232,6 @@ int intel_init_vebox_ring(struct drm_device *dev) ring->signal_mbox[VCS] = GEN6_VVESYNC; ring->signal_mbox[BCS] = GEN6_BVESYNC; ring->signal_mbox[VECS] = GEN6_NOSYNC; - ring->init = init_ring_common; return intel_init_ring(dev, ring); }