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[1/4] drm/i915/bdw: Set initial rps freq to RP1

Message ID 1396311499-27457-1-git-send-email-benjamin.widawsky@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Widawsky April 1, 2014, 12:18 a.m. UTC 
Programming it outside of the rp0-rp1 range is considered a programming
error. Since we do not know that the previous value would actually be in
the range, program something we've read from the hardware, and therefore
know will work.

This is potentially an issue for platforms whose ranges are outside the
norms given in the programming guide (ie. early silicon)

v2: Use RP1 instead of RPn

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Chris Wilson April 1, 2014, 8:21 a.m. UTC | #1 
On Mon, Mar 31, 2014 at 05:18:16PM -0700, Ben Widawsky wrote:
> Programming it outside of the rp0-rp1 range is considered a programming
> error. Since we do not know that the previous value would actually be in
> the range, program something we've read from the hardware, and therefore
> know will work.
> 
> This is potentially an issue for platforms whose ranges are outside the
> norms given in the programming guide (ie. early silicon)
> 
> v2: Use RP1 instead of RPn
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

For my own edification, I read the specs again (because of the RPS
fallout) and the VIDEO_FREQ is simply an alternate to the normal boost
frequency that we can select either manually or via the pcu for media
workloads. We however combine the media workload into overall GPU
activity and so only manage the single RPS frequency.

Therefore this patch is the right thing to do.
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e9a9aef..51ff40e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3284,8 +3284,10 @@  static void gen8_enable_rps(struct drm_device *dev)
 				    rc6_mask);
 
 	/* 4 Program defaults and thresholds for RPS*/
-	I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
-	I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
+	I915_WRITE(GEN6_RPNSWREQ,
+		   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
+	I915_WRITE(GEN6_RC_VIDEO_FREQ,
+		   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
 	/* NB: Docs say 1s, and 1000000 - which aren't equivalent */
 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */