From patchwork Tue Apr 1 18:37:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 3925331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 63E129F2F7 for ; Tue, 1 Apr 2014 18:37:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7FE312022F for ; Tue, 1 Apr 2014 18:37:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 96D0F201FE for ; Tue, 1 Apr 2014 18:37:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2818F6E804; Tue, 1 Apr 2014 11:37:56 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yk0-f172.google.com (mail-yk0-f172.google.com [209.85.160.172]) by gabe.freedesktop.org (Postfix) with ESMTP id 060D86E808 for ; Tue, 1 Apr 2014 11:37:54 -0700 (PDT) Received: by mail-yk0-f172.google.com with SMTP id 200so7873776ykr.31 for ; Tue, 01 Apr 2014 11:37:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jM60vwr1w7C9GKH0bQuK5ysocvADrLCHUOFUFmeBeVE=; b=B7mngZCRjFhXYFD+ZOAVqMvQJ15+BnrCb3P0XqiWJmZVA3utsp7d+f3Ft5f0FYXs0j f7xJa+pJlt2l+2CO6nzAlW+lGZTpiGw9QeReOVAshfplzts5mEjs8YXrqfvqtJkcppFi QwCQs7bTA4v9iNEOJxzJiOiyx4BFo0YXFJucu41gh1a/ikHLuINOHaOmgHg1TrKKpamL 6GDdHQrsh/pz1W4E8gvEgNbZP2wgI93sRZRxxpRHFyFTBb8ZuiBhD1kjIp8wxSB08UR7 72rYcKCZ/IldjEmjxLGIm7JTgrwp58Dx8Q4Wbg5zbyoO7hnR68qf9T/RpgXYYuJlZcwB nDsQ== X-Received: by 10.236.129.227 with SMTP id h63mr4245833yhi.148.1396377474498; Tue, 01 Apr 2014 11:37:54 -0700 (PDT) Received: from localhost.localdomain ([177.42.1.121]) by mx.google.com with ESMTPSA id t58sm31738185yho.20.2014.04.01.11.37.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Apr 2014 11:37:54 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 1 Apr 2014 15:37:22 -0300 Message-Id: <1396377447-2177-15-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1396377447-2177-1-git-send-email-przanoni@gmail.com> References: <1396377447-2177-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 14/19] drm/i915: enable SDEIER later X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-3.9 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni On the preinstall stage we should just disable all the interrupts, but we currently enable all the south display interrupts due to the way we touch SDEIER at the IRQ handlers (note: they are still masked and our IRQ handler is disabled). Instead of doing that, let's make the preinstall stage just disable all the south interrupts, and do the proper interrupt dance/ordering at the postinstall stage, including an assert to check if everything is behaving as expected. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1f601ef..0b03c55 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2875,13 +2875,24 @@ static void ibx_irq_preinstall(struct drm_device *dev) if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) I915_WRITE(SERR_INT, 0xffffffff); +} - /* - * SDEIER is also touched by the interrupt handler to work around missed - * PCH interrupts. Hence we can't update it after the interrupt handler - * is enabled - instead we unconditionally enable all PCH interrupt - * sources here, but then only unmask them as needed with SDEIMR. - */ +/* + * SDEIER is also touched by the interrupt handler to work around missed PCH + * interrupts. Hence we can't update it after the interrupt handler is enabled - + * instead we unconditionally enable all PCH interrupt sources here, but then + * only unmask them as needed with SDEIMR. + * + * This function needs to be called before interrupts are enabled. + */ +static void ibx_irq_pre_postinstall(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (HAS_PCH_NOP(dev)) + return; + + WARN_ON(I915_READ(SDEIER) != 0); I915_WRITE(SDEIER, 0xffffffff); POSTING_READ(SDEIER); } @@ -3077,6 +3088,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) dev_priv->irq_mask = ~display_mask; + ibx_irq_pre_postinstall(dev); + GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); gen5_gt_irq_postinstall(dev); @@ -3265,6 +3278,8 @@ static int gen8_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + ibx_irq_pre_postinstall(dev); + gen8_gt_irq_postinstall(dev_priv); gen8_de_irq_postinstall(dev_priv);