From patchwork Fri Apr 4 23:12:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 3941351 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id ACFA79F357 for ; Fri, 4 Apr 2014 23:12:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ACA27202FF for ; Fri, 4 Apr 2014 23:12:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CBD5D202A1 for ; Fri, 4 Apr 2014 23:12:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BE906E149; Fri, 4 Apr 2014 16:12:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy3-pub.mail.unifiedlayer.com (gproxy3-pub.mail.unifiedlayer.com [69.89.30.42]) by gabe.freedesktop.org (Postfix) with SMTP id BBF3D6E161 for ; Fri, 4 Apr 2014 16:12:30 -0700 (PDT) Received: (qmail 1627 invoked by uid 0); 4 Apr 2014 23:12:30 -0000 Received: from unknown (HELO CMOut01) (10.0.90.82) by gproxy3.mail.unifiedlayer.com with SMTP; 4 Apr 2014 23:12:30 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by CMOut01 with id lzCR1n00W2UhLwi01zCUbe; Fri, 04 Apr 2014 17:12:29 -0600 X-Authority-Analysis: v=2.1 cv=ZpR+dbLG c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=dA9xJEkoxMwA:10 a=3ROhxo7VqVMA:10 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=D8UYHpqr7UO0KSzToqMA:9 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=IvC0Y5C5g+VLJlrE5g48GUh0EhR4XKLy2o4IFQWw1YU=; b=dEdzFMzze5RxTVgEYZHPpIcynTHEeipgHCP/mFcivSOeN6x6GpmapNCRYwW1E2U9wX7+FLBx/PyvvYaGBKY1YiDd4GauejNBuzYzr99kQaEMuXw7d/q1UeCWrLRYQyXU; Received: from [67.161.37.189] (port=56306 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:CAMELLIA256-SHA:256) (Exim 4.82) (envelope-from ) id 1WWDHe-00016L-Bc for intel-gfx@lists.freedesktop.org; Fri, 04 Apr 2014 17:12:26 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Apr 2014 16:12:12 -0700 Message-Id: <1396653132-908-6-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1396653132-908-1-git-send-email-jbarnes@virtuousgeek.org> References: <1396653132-908-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 6/6] drm/i915/vlv: re-order TX lane reset per latest spec X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is supposed to fix some eDP PPS issues on some platforms. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 98cf24f..34d01be 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1844,6 +1844,7 @@ static void vlv_enable_dp(struct intel_encoder *encoder) struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct intel_digital_port *dport = dp_to_dig_port(intel_dp); struct drm_device *dev = encoder->base.dev; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct drm_i915_private *dev_priv = dev->dev_private; uint32_t dp_reg = I915_READ(intel_dp->output_reg); @@ -1855,6 +1856,11 @@ static void vlv_enable_dp(struct intel_encoder *encoder) if (!is_edp(intel_dp)) intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_edp_panel_on(intel_dp); + mutex_lock(&dev_priv->dpio_lock); + vlv_dpio_write(dev_priv, intel_crtc->pipe, VLV_PCS_DW0(dport->port), + DPIO_PCS_TX_LANE2_RESET | + DPIO_PCS_TX_LANE1_RESET); + mutex_unlock(&dev_priv->dpio_lock); vlv_wait_port_ready(dev_priv, dport); edp_panel_vdd_off(intel_dp, true); intel_dp_complete_link_train(intel_dp); @@ -1918,9 +1924,6 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) /* Program Tx lane resets to default */ mutex_lock(&dev_priv->dpio_lock); - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), - DPIO_PCS_TX_LANE2_RESET | - DPIO_PCS_TX_LANE1_RESET); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |