From patchwork Tue Apr 8 17:47:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Previte X-Patchwork-Id: 3950171 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4573D9F499 for ; Tue, 8 Apr 2014 17:48:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 647D3203B5 for ; Tue, 8 Apr 2014 17:48:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 87B8F203AC for ; Tue, 8 Apr 2014 17:47:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 293C66E4E2; Tue, 8 Apr 2014 10:47:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f179.google.com (mail-pd0-f179.google.com [209.85.192.179]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C9AC6E4E2 for ; Tue, 8 Apr 2014 10:47:57 -0700 (PDT) Received: by mail-pd0-f179.google.com with SMTP id w10so1314556pde.38 for ; Tue, 08 Apr 2014 10:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3xw//EwarPGMKi8Ew/qDEIEVynEn6CXR9/yjnoDSWGw=; b=cFBAQryNI25ty9nRI+9EUs4RIjTAeF9HS67m9nktnQne43ijk6sOcdTfpYAZgXdDee ZKNAF6gG7gF+LurMt6veSnzXkq/YAVrz41xd6QyTZk/Jfvla/TQyK9VLE9lA3XNI+sF+ IeFCkvz52muOIpbqa23Db9j3lduowhLA0hwJiuKUiSP3gD0JlF3Fm6E9ri2fvzDFiUSo oAVfaw55TFSM3cfdsP/6fQbDivJmaI57t/900RCXk5shJhbTyowKqf7QVNH2wn34MwQJ Uf6Zmq59Two6F7s8HusG7vy+zBg953zG1xGqh5YeP2TFraNYrX8fjvHb2lBc9OS/57Wj iAkA== X-Received: by 10.68.110.226 with SMTP id id2mr856893pbb.40.1396979277291; Tue, 08 Apr 2014 10:47:57 -0700 (PDT) Received: from localhost.localdomain (ip72-201-95-47.ph.ph.cox.net. [72.201.95.47]) by mx.google.com with ESMTPSA id e6sm5973219pbg.4.2014.04.08.10.47.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 10:47:55 -0700 (PDT) From: Todd Previte To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Apr 2014 10:47:39 -0700 Message-Id: <1396979263-3245-2-git-send-email-tprevite@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396979263-3245-1-git-send-email-tprevite@gmail.com> References: <1396979263-3245-1-git-send-email-tprevite@gmail.com> Subject: [Intel-gfx] [PATCH 1/5] dmr/i915: Displayport - Add a function to set the training pattern X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds a function to set the training pattern for Displayport. This is functionality required to establish more fine-grained control over the Displayport interface, both for operational reliability and compliance testing. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 70 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index adcb9c7..0f0d549 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5303,6 +5303,8 @@ enum punit_power_well { #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) +#define DP_TRAINING_PATTERN_MASK_1P2 0x7 + /* DisplayPort Transport Status */ #define DP_TP_STATUS_A 0x64044 #define DP_TP_STATUS_B 0x64144 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6f767e5..64c9803 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2356,6 +2356,76 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) *DP = (*DP & ~mask) | signal_levels; } +uint32_t +intel_dp_set_training_pattern(uint8_t training_pattern, + struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum port port = intel_dig_port->port; + uint8_t buf[sizeof(intel_dp->train_set) + 1]; + int ret, len; + + uint32_t reg_value, ctrl_reg, tp_select = 0; + uint32_t tp_mask = DP_TRAINING_PATTERN_MASK; + + if (HAS_DDI(dev)) + ctrl_reg = DP_TP_CTL(port); + else + ctrl_reg = intel_dp->output_reg; + + reg_value = I915_READ(ctrl_reg); + + // Check DPCD revision to enable TP3 + if (intel_dp->dpcd[0] >= 12) + tp_mask = DP_TRAINING_PATTERN_MASK_1P2; + + // Mask selection above ensures TP3 does not get enabled for < DP 1.2 + switch (training_pattern & tp_mask) { + case DP_TRAINING_PATTERN_DISABLE: + tp_select = DP_TP_CTL_LINK_TRAIN_NORMAL; + break; + case DP_TRAINING_PATTERN_1: + tp_select = DP_TP_CTL_LINK_TRAIN_PAT1; + break; + case DP_TRAINING_PATTERN_2: + tp_select = DP_TP_CTL_LINK_TRAIN_PAT2; + break; + case DP_TRAINING_PATTERN_3: + tp_select = DP_TP_CTL_LINK_TRAIN_PAT3; + break; + } + + if (HAS_DDI(dev) || (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A))) { + reg_value &= ~(tp_mask << 8); + reg_value |= tp_select; + } + else { + reg_value &= ~(tp_mask << 28); + reg_value |= tp_select << 20; + } + + I915_WRITE(ctrl_reg, reg_value); + POSTING_READ(ctrl_reg); + + buf[0] = training_pattern; + if ((training_pattern & tp_mask) == + DP_TRAINING_PATTERN_DISABLE) { + /* don't write DP_TRAINING_LANEx_SET on disable */ + len = 1; + } else { + /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ + memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); + len = intel_dp->lane_count + 1; + } + + ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, + buf, len); + + return ret == len; +} + static bool intel_dp_set_link_train(struct intel_dp *intel_dp, uint32_t *DP,