From patchwork Tue Apr 8 17:47:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Previte X-Patchwork-Id: 3950201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4AB1ABFF02 for ; Tue, 8 Apr 2014 17:48:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 672F6203B5 for ; Tue, 8 Apr 2014 17:48:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9858C203AC for ; Tue, 8 Apr 2014 17:48:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C7A26E4B1; Tue, 8 Apr 2014 10:48:16 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f180.google.com (mail-pd0-f180.google.com [209.85.192.180]) by gabe.freedesktop.org (Postfix) with ESMTP id 53E296E4EA for ; Tue, 8 Apr 2014 10:48:14 -0700 (PDT) Received: by mail-pd0-f180.google.com with SMTP id v10so1306201pde.25 for ; Tue, 08 Apr 2014 10:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7o3pyCpo/+SsNLYI0qQ/rthd078w3E0SO8AjkAX/+zQ=; b=f9C78N7zFrGQjengi2q29L80VT+qJuFmdMuYKcJYFXRhSDdWOrBHVfXWG59BOpxLKe DJKmN87oCOlS0F693lPTgS5pjpL1Zt6jaCdw+glRJNCsRYpIQJuN0JqOOOyE5FaIyuRw bq+QxctO9EJTWtmP/wyNeD/Oyiyh30xXlPPTqI+IYRkRzFtGDFT9Jp+bnEkA7o+usLnr H1Sq8yR5bv1wRcx1nJRxVyB9I4kY8fEKv++ay4bXZPgwPJ8zHGGCV3Q70+N6VvJLuS5C Y06b9+C8QETMLr6s4lx5YtHZa+nxXbGwzU0xS8zVVLu1y13YaCxJhekv1EsXoZ1EwSU2 ThPA== X-Received: by 10.66.140.104 with SMTP id rf8mr6152399pab.107.1396979294207; Tue, 08 Apr 2014 10:48:14 -0700 (PDT) Received: from localhost.localdomain (ip72-201-95-47.ph.ph.cox.net. [72.201.95.47]) by mx.google.com with ESMTPSA id e6sm5973219pbg.4.2014.04.08.10.48.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 10:48:13 -0700 (PDT) From: Todd Previte To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Apr 2014 10:47:42 -0700 Message-Id: <1396979263-3245-5-git-send-email-tprevite@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396979263-3245-1-git-send-email-tprevite@gmail.com> References: <1396979263-3245-1-git-send-email-tprevite@gmail.com> Subject: [Intel-gfx] [PATCH 4/5] drm/i915: Displayport - Add function for executing a single iteration of clock recovery X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds a function to execute a single iteration of the clock recovery sequence for Displayport. This is functionality required to establish more fine-grained control over the Displayport interface, both for operational reliability and compliance testing. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_dp.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0f0d549..eebc4f2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5304,6 +5304,12 @@ enum punit_power_well { #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) #define DP_TRAINING_PATTERN_MASK_1P2 0x7 +#define DP_CLOCK_RECOVERY_COMPLETE 0x0 +#define DP_CLOCK_RECOVERY_FAILED 0x1 +#define DP_LINK_STATUS_READ_FAILED 0x2 +#define DP_CHANNEL_EQUALIZATION_COMPLETE 0x0 +#define DP_CHANNEL_EQUALIZATION_FAILED 0x1 +#define DP_SYMBOL_LOCK_FAILED 0x1 /* DisplayPort Transport Status */ #define DP_TP_STATUS_A 0x64044 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1209de8..6baa26c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2466,7 +2466,7 @@ intel_dp_set_training_pattern(uint8_t training_pattern, reg_value = I915_READ(ctrl_reg); // Check DPCD revision to enable TP3 - if (intel_dp->dpcd[0] >= 12) + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12) tp_mask = DP_TRAINING_PATTERN_MASK_1P2; // Mask selection above ensures TP3 does not get enabled for < DP 1.2 @@ -2850,6 +2850,34 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp) DP_TRAINING_PATTERN_DISABLE); } +// State-based link training functions +// FIXME: Remove these comments before commit! +uint32_t intel_dp_exec_clock_recovery(struct intel_dp *intel_dp) +{ + uint32_t clock_recovery_status = DP_CLOCK_RECOVERY_FAILED; + uint8_t link_status[DP_LINK_STATUS_SIZE]; + + // Set the training pattern for clock recovery + intel_dp_set_training_pattern(DP_TRAINING_PATTERN_1, intel_dp); + + // Wait for clock recovery time period to expire + drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); + + // Check link status + if (!intel_dp_get_link_status(intel_dp, link_status)) { + clock_recovery_status = DP_LINK_STATUS_READ_FAILED; + goto exit; + } + + // Verify clock recovery is successful + if (intel_dp_verify_link_status(DP_LINK_TRAINING_STATE_CLOCK_REC, + intel_dp->lane_count, link_status)) + clock_recovery_status = DP_CLOCK_RECOVERY_COMPLETE; + +exit: + return clock_recovery_status; +} + static void intel_dp_link_down(struct intel_dp *intel_dp) {